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09-06-2007, 07:52 AM
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Error while Simulation
Hai Frndz,
I Designed a simple flip-flop using vhdl and i created a testbench for that. When i run the simulation for the testbench,it is not giving one bit delay instead when i run the simulation without tetbench it gives one bit delay.Any one can u plz tell me why this happens. sridar |
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