downto vs. to

Hello,
i'm a vhdl-beginner, and a currently have no access to a working
vhdl-environment. i don't understand the order of vectorelements:

signal FooTo: std_logic_vector(0 to 1) = "01"; -- decimal value 2
signal FooDownTo: std_logic_vector (1 downto 0) = "10"; -- decimal
value 2

what is the value of FooTo(1) and of FooDownTo(1) respectvely?

FooTo(1) = ....
FooDownTo(1) = ....

Thanks for your help!

Fabian

Fabian

I have been thinking about this also today.

I am pretty sure that they are the same value,
that is decimal two. I believe that the difference
in the to and downto relates mostly to how the
vectors will be written and how they show in the
simulation software.

We will see downto more often than "to" because
we will want to write our binary numbers with the
0th element on the far right.

When I began VHDL I thought the best idea was to
write downto for everything. However when I started
simulating time delays, fifos, and memory, it
seemed better to start using the "to" because in
these models you want to see the first thing that
happens in the leftmost position. And you want to
see memories with the 0th element listed first.

Today I put downto numbers into my "to" line delays
without any apparent problem as long as the lengths
matched.

I don't know anything about math library functions.

Anybody want to correct me on any of this, feel free.

Brad Smallridge
Ai Vision


"Fabian" <> wrote in message
news: oups.com...
> Hello,
> i'm a vhdl-beginner, and a currently have no access to a working
> vhdl-environment. i don't understand the order of vectorelements:
>
> signal FooTo: std_logic_vector(0 to 1) = "01"; -- decimal value 2
> signal FooDownTo: std_logic_vector (1 downto 0) = "10"; -- decimal
> value 2
>
> what is the value of FooTo(1) and of FooDownTo(1) respectvely?
>
> FooTo(1) = ....
> FooDownTo(1) = ....
>
> Thanks for your help!
>
> Fabian
>

Brad Smallridge

Hi!

> signal FooTo: std_logic_vector(0 to 1) = "01"; -- decimal value 2
> signal FooDownTo: std_logic_vector (1 downto 0) = "10"; -- decimal
> value 2

A std_logic_vector doesn't have a decimal value per se. You can just
convert it to a decimal value by interpreting its contents.

The elements of the constant string are assigned to indice inside the
std_logic_vector based on the order in that they are written.

FooTo(0) is '0' and FooTo(1) is '1' because
* '0' is the leftmost value of the string and
0 is the left index of the vector
* '1' is the rightmost value of the string and
1 is the right index of the vector
FooDownTo(1) is '1', FooDownTo(0) is '0' for the same reasons.


Now coming back to decimal values, the attached code yields that
FooTo_nat is 1 and FooDownTo_nat is 2 since the numeric_std conversion
function to_integer considers the leftmost element of an unsigned value
as the MSB and the rightmost element as the LSB.
Using (... to ...) vectors can be mind-boggling in the first place
(especially for integer arithmetics) but they're straight forward once
you accept that 'left' and 'right' are relevant but not 'upper' and 'lower'.

HTH
Arnim


-----------------------------8<-----------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity range_to is

end range_to;

architecture behav of range_to is

signal FooTo: std_logic_vector(0 to 1) := "01";
signal FooDownTo: std_logic_vector (1 downto 0) := "10";

signal FooTo_nat : natural;
signal FooDownTo_nat : natural;

begin

FooTo_nat <= to_integer(unsigned(FooTo));
FooDownTo_nat <= to_integer(unsigned(FooDownTo));

process
begin
wait for 1 ns;
wait;
end process;

end behav;

Arnim

Fabian <> writes:

> Hello,
> i'm a vhdl-beginner, and a currently have no access to a working
> vhdl-environment. i don't understand the order of vectorelements:
>
> signal FooTo: std_logic_vector(0 to 1) = "01"; -- decimal value 2
> signal FooDownTo: std_logic_vector (1 downto 0) = "10"; -- decimal
> value 2
>

You can't say that either of these has decimal value of '2', as they
are logic_vectors, which have no numerical meaning.

You have to use ieee.numeric_std.all and then specify them as signed
or unsigned to treat them as numbers.

Try this test:

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity numeric_test is

end entity numeric_test;

architecture test of numeric_test is
signal unsigned_up : unsigned(0 to 3) := (others => '0');
signal unsigned_dn : unsigned(3 downto 0) := (others => '0');
begin -- architecture test
testproc : process is
begin -- process testproc
for i in 0 to 17 loop
wait for 10 ns;
unsigned_up <= unsigned_up + 1;
unsigned_dn <= unsigned_dn + 1;
end loop; -- i
wait;
end process testproc;


end architecture test;


You'll see that both vectors count up the same. This means that the
*leftmost* bit is the MSB, and the *rightmost* bit is the LSB,
irrespective of the direction of the vector.

This means that "to" is used for big-endian buses (like the PowerPC
uses) and "downto" for little-endian buses (like Intel and most of the
rest of the world uses).

Personally, I use downto for everything unless I have good reason not
to (PowerPCs being one of them...)


> what is the value of FooTo(1) and of FooDownTo(1) respectvely?
>
> FooTo(1) = ....
> FooDownTo(1) = ....
>

'1' in both cases, but it will have the value of '2' in the "downto"
case and '1' in the "to" case, assuming you change the type to
unsigned.

> Thanks for your help!
>

Hope I did, not just cause more confusion!

Cheers,
Martin

--

TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Martin Thompson

Hey Fabian,
I reread your post and find that I didn't answer your question.
I ran this simulation with ModelSim and both a and b are 1.
Brad Smallridge
AiVision

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
end top;

architecture Behavioral of top is

signal FooTo: std_logic_vector(0 to 1) ;
signal FooDownTo: std_logic_vector (1 downto 0) ;
signal a : std_logic;
signal b : std_logic;

begin

FooTo <= "01";
FooDownTO <= "10";
a <= FooTo(1);
b <= FooDownTo(1);

end Behavioral;

Brad Smallridge