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VHDL - Ext. Clock trigger inside Full-Moore state machine problem |
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08-28-2007, 05:07 PM
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Ext. Clock trigger inside Full-Moore state machine problem
Hi
It is o.k. to use clock event (rise/fall time check) inside Full-Moore state machine? I try to implement it but it's fail in synthesis. I need to wait for Ext. Clock as a trigger inside my state machine? Do u have any offers how to implement it right? Thanks klior |
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