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VHDL question - strings in generics...

 
 
Russell
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      08-19-2007
I used a string in a generic with the '&' operator (as shown in the
code fragment below), but it does not concatenate (ignores the part
after the &)

Do you know if concatenation is not allowed for generics?

entity mux is

generic (

PartNo : string := "12345" & "ABC"

);

port (

TxClk : in std_logic;

Etc...

Gives PartNo as "12345"

 
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Mark McDougall
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      08-20-2007
Russell wrote:

> Do you know if concatenation is not allowed for generics?


Probably depends on your synthesis tool.

I've used string concatenation in constants with any problems, but never
generics as far as I can recall...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
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Russell Russell is offline
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Join Date: Aug 2007
Posts: 6
 
      08-20-2007
I had defined it (also) in the test bench at the top level of the simulation
 
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Mike Treseler
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      08-20-2007
Russell wrote:
> I used a string in a generic with the '&' operator (as shown in the
> code fragment below), but it does not concatenate (ignores the part
> after the &)


That tool is broken. Report the bug.

-- Mike Treseler
 
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