Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Adding two registers A and B in vhdl

Thread Tools

Adding two registers A and B in vhdl

Haai Haai is offline
Junior Member
Join Date: Aug 2007
Posts: 5
I created two registers (A and B), I want to add them together and store the answer in A.
Is it possible to use operators such as + - x?
Can any body help me to accomplish this task?

library ieee;
use ieee.std_logic_1164.all;

entity toets3 is
data : in std_ulogic_vector(7 downto 0);
clk : in std_logic;
Q : out std_ulogic_vector(7 downto 0));
end toets3;

architecture a of toets3 is
signal A,B : std_ulogic_vector (7 downto 0);

process (clk)
if rising_edge(clk) then
A <= A + B;
end if;
end process;
Q <= A;
end a;
Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Adding two registers A and B in vhdl Haai Hardware 0 08-18-2007 03:56 PM
Is it possible to infer double data rate registers from VHDL code? VHDL 5 08-16-2007 03:40 AM
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
jtag/ATPG and read-only registers Calvin VHDL 0 11-23-2005 04:43 AM
About Latches and Registers was (When do I always put a "else NULL"statement in my VHDL code?) Ingmar Seifert VHDL 0 09-14-2003 07:57 PM