Adding two registers A and B in vhdl

I created two registers (A and B) I want to add them together and store the answer in A.
Is it possible to use operators such as + - x?
Can any body help me to accomplish this task?

library ieee;
use ieee.std_logic_1164.all;

entity toets3 is
port(
data : in std_ulogic_vector(7 downto 0);
clk : in std_logic;
Q : out std_ulogic_vector(7 downto 0));
end toets3;

architecture a of toets3 is
signal A,B : std_ulogic_vector (7 downto 0);

begin
process (clk)
begin
if rising_edge(clk) then
A <= A + B;
end if;
end process;
Q <= A;
end a;

Haai