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xilinx simprim compilation error

 
 
Pinhas
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      08-14-2007
Hello
I am tring to compile it /simprim_VITAL.vhd with GHDL (free VHDL
simulator) and get errors regarding:
.....
simprim_VITAL.vhd:153574:57: variable "write_b_read_a" is not visible
here

This is a vriable declared in process with strange way:
VITALBehavior : process

variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
.... variable Write_B_Read_A : memory_collision_type :=
Write_B_Read_A;
....

My question why to initialize with the same value (Write_B_Read_A).

 
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Georg Acher
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      08-14-2007
Pinhas <(E-Mail Removed)> writes:
>Hello
>I am tring to compile it /simprim_VITAL.vhd with GHDL (free VHDL
>simulator) and get errors regarding:
>....
>simprim_VITAL.vhd:153574:57: variable "write_b_read_a" is not visible
>here
>
>This is a vriable declared in process with strange way:
> VITALBehavior : process
>
> variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
>... variable Write_B_Read_A : memory_collision_type :=
>Write_B_Read_A;
>...
>
>My question why to initialize with the same value (Write_B_Read_A).


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