Ei guyz. I'm still a noob in VHDL. I know this code is quite simple but it doesn't work (don't have any idea why).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity oneShot_tryA is
port (CLOCK : in STD_LOGIC;
ENABLER_A : in STD_LOGIC;
OUTPUT : buffer STD_LOGIC);
end oneShot_tryA;
architecture OneShot_TryA_ARCH of oneShot_tryA is
signal counter : STD_LOGIC:='0';
begin
process (CLOCK)
begin
if rising_edge(CLOCK) then
if ENABLER_A='1' or OUTPUT='1' then
OUTPUT <= not counter;
end if;
elsif OUTPUT='1' then
OUTPUT <= not counter;
counter <= '1';
elsif ENABLER_A='0' then
counter <= '0';
end if;
end process;
end OneShot_TryA_ARCH;
It has this error message => "Signal counter cannot be synthesized, bad synchronous description."
HELP! Thanx
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