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2 Multiplied clock sync.

klior klior is offline
Junior Member
Join Date: Jul 2007
Posts: 2
I have got 2 Multiplied External clock (40MHz & 10MHz) that reach my FPGA.
I assume that they are Synchronize each other.
The 10MHZ is used as Main Trigger and the 40MHz as the actual trigger (so I need to sample 4 times in the 10MHz period)
Is anyone had any idea how to implement it in VHDL or Block design?
If u can recommend about particular article it will be great too.
Thanks a lot
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