Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Concurrent assignment Modelsim problem. Please, need help ASAP.

Thread Tools

Concurrent assignment Modelsim problem. Please, need help ASAP.

jason12 jason12 is offline
Junior Member
Join Date: Jul 2007
Posts: 1

I am trying to use someone else code and having issues in modelsim.

Here it is.

signal abc : std_logic_vector(10 downto 0);

abc(10 downto 9) <= "00";
abc(8 downto 0) <= "111111111";

After compilation and simulation the VCD file contains abc(10) and abc( only.

If I change it to
abc(10 downto 0) <= "00111111111";
Modelsim is happy and VCD has full vector.

The problem is that the original code is more complicated than the one shown as an example. Plus I am not at liberty to change it (not mine). Is there a way to force Modelsim to compile/simulate the original assignments right?

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Concurrent signal assignment vs. port mapping Torsten Landschoff VHDL 1 07-28-2008 01:29 PM
problems locating the concurrent EDU.oswego.cs.dl.util.concurrent package Pep Java 6 08-16-2005 07:26 AM
Concurrent Assignment Taras_96 VHDL 6 04-04-2005 01:01 AM
help with modelsim error (delay in signal assignment must be ascending) ra VHDL 3 08-04-2004 11:31 AM
Concurrent assignments to std_ulogic_vector slice is OK with ModelSim Nicolas Matringe VHDL 9 06-14-2004 10:10 PM