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Concurrent assignment Modelsim problem. Please, need help ASAP.

 
 
jason12 jason12 is offline
Junior Member
Join Date: Jul 2007
Posts: 1
 
      07-29-2007
Hi,

I am trying to use someone else code and having issues in modelsim.

Here it is.

signal abc : std_logic_vector(10 downto 0);
......

abc(10 downto 9) <= "00";
abc(8 downto 0) <= "111111111";


After compilation and simulation the VCD file contains abc(10) and abc( only.

If I change it to
abc(10 downto 0) <= "00111111111";
Modelsim is happy and VCD has full vector.


The problem is that the original code is more complicated than the one shown as an example. Plus I am not at liberty to change it (not mine). Is there a way to force Modelsim to compile/simulate the original assignments right?

Thanks
 
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