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General question on access SRAM

 
 
picnanard picnanard is offline
Junior Member
Join Date: Mar 2007
Posts: 19
 
      07-24-2007
I want control the read and write (SRAM single data port) with FPGA I want stick a read cycle after write cycle. See below
CS ----\_________________/------
RD ----\_______/-----------------
WR -------------\________/-----------

According your experience
Can I do that?
The data sheet indicate the data still on the bus 8ns after the RD raising edge.
 

Last edited by picnanard; 07-24-2007 at 12:22 PM..
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