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In Verilog, I would do

assign my_probe = i_mydesign.i_submodule.mult_en;

I checked my textbooks but difficult to find equivalents in VHDL.

Thanks in advance.

Does VHDL support `include statement?

I was used to write tables and functions in a separate file and use `include
in
verilog design, in order to "put everything in single file" while avoiding
large
filesizes, one example is 1000+-line look-up tables.

"G Iveco" <> wrote in message
news:f7uhrh$l0l$...
> In Verilog, I would do
>
> assign my_probe = i_mydesign.i_submodule.mult_en;
>
> I checked my textbooks but difficult to find equivalents in VHDL.
>
> Thanks in advance.

Hierarchical references will be supported in the upcoming VHDL2006, see Jim
Lewis presentation at
http://www.synthworks.com/papers/vhd...2006_color.pdf

Most, if not all simulator have some non-standard support for this, if you
are using Modelsim then have a look at signalspy,

Hans
www.ht-lab.com



>
>

"G Iveco" <> wrote in message
news:f7uk1n$l2c$...
> Does VHDL support `include statement?
>
> I was used to write tables and functions in a separate file and use
> `include in
> verilog design, in order to "put everything in single file" while avoiding
> large
> filesizes, one example is 1000+-line look-up tables.

Look up library, use and package in your VHDL textbook (or google)

Hans
www.ht-lab.com

>
>
>

On Jul 22, 10:17 am, "G Iveco" <G.Iv...@google.com> wrote:
> Does VHDL support `include statement?
>
> I was used to write tables and functions in a separate file and use `include
> in
> verilog design, in order to "put everything in single file" while avoiding
> large
> filesizes, one example is 1000+-line look-up tables.


VHDL doesn't support 'include .However google "vunit" .This might
help.

Probing of internal signals is also not supported by the language but
individual simulators provide this function.
For ModelSim, google "SingalSpy".
For NcSim, google "nc_mirror"

regards,
Anupam Jain

wrote:
> On Jul 22, 10:17 am, "G Iveco" <G.Iv...@google.com> wrote:
>> Does VHDL support `include statement?
>>
>> I was used to write tables and functions in a separate file and use `include
>> in
>> verilog design, in order to "put everything in single file" while avoiding
>> large
>> filesizes, one example is 1000+-line look-up tables.
>
>
> VHDL doesn't support 'include .However google "vunit" .This might
> help.
>
> Probing of internal signals is also not supported by the language but
> individual simulators provide this function.
> For ModelSim, google "SingalSpy".
> For NcSim, google "nc_mirror"

As an alternative, you could consider placing the signal in a package, and use
that package both in your design and in your test bench/case.

Kind regards,

Pieter Hulshoff

<> wrote in message
news: ps.com...
> On Jul 22, 10:17 am, "G Iveco" <G.Iv...@google.com> wrote:
>> Does VHDL support `include statement?
>>
>> I was used to write tables and functions in a separate file and use
>> `include
>> in
>> verilog design, in order to "put everything in single file" while
>> avoiding
>> large
>> filesizes, one example is 1000+-line look-up tables.
>
>
> VHDL doesn't support 'include .However google "vunit" .This might
> help.

vunit? that is PSL,

Hans
www.ht-lab.com


>
> Probing of internal signals is also not supported by the language but
> individual simulators provide this function.
> For ModelSim, google "SingalSpy".
> For NcSim, google "nc_mirror"
>
> regards,
> Anupam Jain
>