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Dual Port RAM Simulation

 
 
Scott
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Posts: n/a
 
      07-18-2007
Hello,

I'm having a simulation issue with the code below. I got tired of
using Coregen to generate dual port rams of various configurations, so
I decided to come up with parameterized, inferred dpram. It
synthesizes correctly using Synplicity, using BlockRams in Xilinx
Virtex devices. However, when I tried to simulate using ModelSim, the
memory array does not get written. The two processes that write to
the array seems to conflict with one another. Is there a way to
correct this? Thanks.


************************************************** ******************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dpram_cc is
generic
(
width : integer:=8;
depth : integer:=256;
addr : integer:=8
);

port
(
clk : in std_logic;

a_en : in std_logic; -- port a enable
a_wr : in std_logic; -- port a write
a_addr : in std_logic_vector(addr-1 downto 0); -- port a
address
a_data_in : in std_logic_vector(width-1 downto 0); -- port a
data in
a_data_out : out std_logic_vector(width-1 downto 0); -- port a
data out

b_en : in std_logic; -- port b
enable
b_wr : in std_logic; -- port b
write
b_addr : in std_logic_vector(addr-1 downto 0); -- port b
address
b_data_in : in std_logic_vector(width-1 downto 0); -- port b
data in
b_data_out : out std_logic_vector(width-1 downto 0) -- port b
data out
);

end dpram_cc;

architecture rtl of dpram_cc is

type mem is array (0 to depth-1) of std_logic_vector(width-1 downto
0);

signal ram : mem;

-- xilinx synthesis attribute for using block rams
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : signal is "block_ram";

begin

--
************************************************** ***********************
-- port a write
--
************************************************** ***********************
process (clk)
begin
if (clk'event and clk='1') then
if (a_wr = '1') and (a_en = '1') then
ram(to_integer(unsigned(a_addr))) <= a_data_in;
end if;
end if;
end process;

--
************************************************** ***********************
-- port a read
--
************************************************** ***********************
process (clk)
begin
if (clk'event and clk='1') then
if (a_en = '1') then
a_data_out <= ram(to_integer(unsigned(a_addr)));
end if;
end if;
end process;

--
************************************************** ***********************
-- port b write
--
************************************************** ***********************
process (clk)
begin
if (clk'event and clk='1') then
if (b_wr = '1') and (b_en = '1') then
ram(to_integer(unsigned(b_addr))) <= b_data_in;
end if;
end if;
end process;

--
************************************************** ***********************
-- port a read
--
************************************************** ***********************
process (clk)
begin
if (clk'event and clk='1') then
if (b_en = '1') then
b_data_out <= ram(to_integer(unsigned(b_addr)));
end if;
end if;
end process;

end rtl;

 
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