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Dear all,

I need to simulate my design with a design whihc was done already in
verilog. Design in Verilog will communicate with the Design in VHDL.

I did simulation of my Design in VHDL using a test bench, but for
practical reasons I need to used the other design in same test.

HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??

PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??

thanks in advance,

mirza

"Mirza" <> wrote in message
news: ps.com...
> Dear all,
>
> I need to simulate my design with a design whihc was done already in
> verilog. Design in Verilog will communicate with the Design in VHDL.
>
> I did simulation of my Design in VHDL using a test bench, but for
> practical reasons I need to used the other design in same test.
>
> HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??
>
> PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??

Please don't shout

Most if not all commercial simulators allow you to mix and match any HDL
language (Verilog, VHDL, SystemC, SystemVerilog) at any level of the
hierarchy. It is just a question of paying the dosh for that extra language
feature and reading the section on mix-language simulation.

Hans
www.ht-lab.com


>
> thanks in advance,
>
> mirza
>

"Mirza" <> wrote in message
news: ps.com...
> Dear all,
>
> I need to simulate my design with a design whihc was done already in
> verilog. Design in Verilog will communicate with the Design in VHDL.
>
> I did simulation of my Design in VHDL using a test bench, but for
> practical reasons I need to used the other design in same test.
>
> HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??
>
> PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??
>

1. If not already obtained, pay the money necessary to get mixed language
support from your simulator tool of choice.
2. Read the user's guide from that simulator tool on how to instantiate the
Verilog component into a VHDL design (or vice versa).
3. Do what it says.

For what it's worth, instantiating a Verilog module into VHDL source using
Modelsim is completely transparent. You add the Verilog source file to your
project and compile it (as you would with any VHDL file) and then simply
instantiate the module in the same way you would an entity. The following
shows the VHDL source you would use to instantiate a VHDL and a Verilog
widget.

DUT1 : entity work.MyVhdlEntity generic map(...) port map(...);
DUT 2: entity work.MyVerilogModule generic map(...) port map(...);

Usually the only issues that come up in mixed language sims is not how to
plop down the module in the code but if there are 'non-standard' signal
types on the interfaces. If everything is std_ulogic/std_ulogic_vector (and
their Verilog counterparts) as is typically the case, then there should be
no issues.

KJ

[scottcarl]

Mizra,

You should be wary of the Modelsim mixed signal simulation. Simulation will work, however, you can only see the signals correlating to your top-level testbench. Meaning if your tb is VHDL, then you won't be able to see in you waveform viewer any Verilog signals. It's a pretty awful tool for mixed simulation, even the soupped up SE version. I would recommend something besides Modesim, Active-HDL from Aldec perhaps.

I speak from painful experience,
Scott

But then, why bother to pay the extra dollars/euros or whatever when
Aldec's simulators offer mixed language as standard and that for very
realistic pricing.

C. G. wrote:

> But then, why bother to pay the extra dollars/euros or whatever when
> Aldec's simulators offer mixed language as standard and that for very
> realistic pricing.

But not with a realistic level of quality. At least not for me.

I've tried the Riviera simulator and found that it could not compile my
existing verification libraries (VHDL only). Numerous segmentation
violations and hang situations occurred. From the eight testcases that I
sent to Aldec, four where segmentation violations, one hang situation and
three "normal" error messages (due to unsupported language constructs).

The feedback from Aldec was quite fast. Within a week or so I got a new
version with my reported issues fixed. However, now I found other issues
(still in the compilation stage) and I did not want to spend more time.

I guess sending the complete verification environment (all libraries) is the
only way to get Riviera working for me. In fact, that is what the AE
suggested. I didn't want to go down that road, not knowing where it would
lead to, how long it would be and how much time it would cost me.

So that is why we keep on paying the extra bucks.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

Paul Uiterlinden wrote:
>
> I've tried the Riviera simulator and found that it could not compile my
> existing verification libraries (VHDL only). Numerous segmentation
> violations and hang situations occurred. From the eight testcases that I
> sent to Aldec, four where segmentation violations, one hang situation and
> three "normal" error messages (due to unsupported language constructs).
>

I'll just say that I just started using Riviera (version 2007.06) about
a month ago, after having used Modelsim for years. I am running some
fairly large and complex (mixed, though mostly VHDL) designs through it.
I had no problems with compiling anything. I did have one problem with
one particular piece of code with a crash when trying to initialize the
simulator, but I quickly found a workaround. And once reported to Aldec,
they quickly fixed it, and I have had no such issues since.

Like all engineering software, it has its "features". But have gotten to
like it, and it does simulate fast. And for independent consultants,
Aldec has some nice discounts. I have now switched to it as my main
simulator.

"C. G." <> wrote in message
news:f7ggpn$me8$02$...
> But then, why bother to pay the extra dollars/euros or whatever when
> Aldec's simulators offer mixed language as standard and that for very
> realistic pricing.

When I contacted Aldec for an evaluation-license and pricing (Active-HDL),
their price-list showed single-language (VHDL or Verilog) at roughly $5000,
and mixed-HDL at roughly $9500.

What pricing did you get, and what makes it more 'realistic' than say,
Modelsim PE Designer Edition? (Which is in roughly the same range.)

Xilinx User wrote:
> "C. G." <> wrote in message
> news:f7ggpn$me8$02$...
>> But then, why bother to pay the extra dollars/euros or whatever when
>> Aldec's simulators offer mixed language as standard and that for very
>> realistic pricing.
>
> When I contacted Aldec for an evaluation-license and pricing (Active-HDL),
> their price-list showed single-language (VHDL or Verilog) at roughly $5000,
> and mixed-HDL at roughly $9500.
>
> What pricing did you get, and what makes it more 'realistic' than say,
> Modelsim PE Designer Edition? (Which is in roughly the same range.)
>

Well, for one thing, no Linux version of Modelsim PE. That means I
cannot use Modelsim PE. And another factor would be the relative
performance of Riviera versus Modelsim PE. Since I have never used
Modelsim PE, I don't know how fast it is. I do know that Riviera is
quite fast. Don't compare on price alone.

But yes, when I purchased Riviera recently, I paid extra for mixed
language support.

Duane Clark wrote:

> I'll just say that I just started using Riviera (version 2007.06) about
> a month ago, after having used Modelsim for years. I am running some
> fairly large and complex (mixed, though mostly VHDL) designs through it.
> I had no problems with compiling anything.

The problems I saw where all in the verification environment. This is quite
a complex environment, using the VHDL language to its limits. Mostly
behavioral constructs. I guess that side is not that well covered in
Riviera.

> Like all engineering software, it has its "features". But have gotten to
> like it, and it does simulate fast.

That's interesting. Thanks for the information.

May be, just may be I should take Riviera in (re)consideration again.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.