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"IF" condition & STD_LOGIC_VECTOR

 
 
ontos ontos is offline
Junior Member
Join Date: Mar 2007
Posts: 12
 
      06-27-2007
Hi!
I have one question about IF condition and STD_LOGIC_VECTOR compatibillities. So, I try to compare two vectors: A and B. They are 32 bits long:

Process(...)
begin
..
IF (A <= B) THEN....
..
END IF;
..
end process;

Functions <=, <,... for the vectors is implemented in package "unsigned".
Multisim don't give any error, but this comparison just don't work. All logic is goot, just condition...Have you any thoughts?

Thanks
 
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