«

On Jun 28, 3:04 am, "devices" <me@home> wrote:
> > U didn't said that isda was a the same as clk. I said that u can apply
> > 'always @ (negedge xxx)' only to clock signal. Usually in FPGAs there is
> > only one dedicated clock line that's why when u try to use more then one
> > clock synthesis gives u warnings.
>
> > When in the same project u use always @ (posedge signal1) and always @
> > (posedge signal2) this require 2 clock lines - maybe this is your problem.
>
> > Best regards
>
> > Maciek Wojtynski
>
> With both clk and isda as clocking signals, the timing
> analyzer computed the shortest and longest path, the
> shortest and longest delay and, as a warning, concluded
> that the circuit may not operate.

Why two clocks?

-a

"Andy Peters" <> wrote in message
news: ups.com...

> > With both clk and isda as clocking signals, the timing
> > analyzer computed the shortest and longest path, the
> > shortest and longest delay and, as a warning, concluded
> > that the circuit may not operate.
>
> Why two clocks?
>
> -a

ISDA is used locally to drive a flip flop clock. I
needed to detect its edges. Well, a flip flop clock
input would do that. The falling and rising edges of
SDA, in i2c, trigger the start and end conditions while
SCL holds high. So once the always block is triggered,
to detected the condition is just a matter of checking
SCL. I didn't invent anything. I had an application note
where the edges of SDA and mostly SCL were used
like that. I don't remember the AppNote case, but in
my case ISDA is internally generated (that's why
I-SDA) by my humble i2c master. I'm using the
Quartus II timing analyzer and i guess the ISDA's way
of driving the flip flop is what Altera calls a Registered
Clock and the analyzer might complain with warnings.

I'm not really interested in the ISDA thing now (as
i said i ended up in using a synchronous edge detector),
but i find that with Quartus' timing analyzer this kind of
issues arises frequently, even with clock dividers. Altera
explains why:

http://www.altera.com/literature/wp/...ngAnalysis.pdf

The key concept of the document is that the analyzer
does its best to check every possible issue in timing.
I guess that some of the warnings might be ignored or
you could instruct the analyzer on what you are doing
by setting up the analysis with detailed contraints. I'll
have to find out a way (or a way out to set a threshold
above or under which i can shrug my shoulder.

--

"devices" <me@home> wrote in message
news:468a5de0$0$36441$ ...

> I'm not really interested in the ISDA thing now (as
> i said i ended up in using a synchronous edge detector),
> but i find that with Quartus' timing analyzer this kind of
> issues arises frequently, even with clock dividers. Altera
> explains why:
>
> http://www.altera.com/literature/wp/...ngAnalysis.pdf
>
> The key concept of the document is that the analyzer
> does its best to check every possible issue in timing.
> I guess that some of the warnings might be ignored or
> you could instruct the analyzer on what you are doing
> by setting up the analysis with detailed contraints. I'll
> have to find out a way (or a way out to set a threshold
> above or under which i can shrug my shoulder.


I've finally managed to make the Analyzer smile.
As i said, either you ignore the warnings or you declare
all the clocks and their operating points in the setup.

I decided to provide the details to Analizer's setup.

1) system clk
2) pll clk (i don't need it right now. Just a test)
3) baud rate generator (baud*16)

That's ok.

In this case if i had ignored the warnings it would have
been the same, but i wanted to gain some knowledge.

NOTES

1) I had already specified the details for the system clk.

2) The pll clk doesn't drive anything at the moment (no
warning anyway).

3) The baud rate generator used to give me warnings.
Working like a clock divider it was detected as a Ripple
Clock. The Analizer detected it as a clock but had no info
about it, so according to its own calculation it reported some
hold time violation. Now that i provided its parameters i get
no more warnings.