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Hi All,
Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL
-Parag

wrote:

> Is a signal in VHDL supposed to mean that we have a source in the
> entity somewhere. Can there be any Verilog analogy to the signal in
> VHDL

yes, it's called "wire" in Verilog.

--
Frank Buss,
http://www.frank-buss.de, http://www.it4-systems.de

As far as I believe, there is no concept of a single physical wire in
VHDL ,
what signals could have possibly meant and what I feel after reading
about it is that,it is a source in an entity. ( if we are to extentd
the concept of source to sink in VHDL )

:
> As far as I believe, there is no concept of a single physical wire in
> VHDL ,
> what signals could have possibly meant and what I feel after reading
> about it is that,it is a source in an entity. ( if we are to extentd
> the concept of source to sink in VHDL )

It Can be either a wire or reg, if I use verilog analogy. It depends
on the usage.
Pinhas
http://bknpk.no-ip.biz
http://bknpk.no-ip.biz/usb_1.html

wrote:

> As far as I believe, there is no concept of a single physical wire in
> VHDL ,

In VHDL you can define input and output signals in the "port" section. If
you use "signal" inside a "architecture" section in VHDL, it is really the
same like Verilog, because "wire" is not a physical wire in verilog, too
and doesn't need to be a single wire, e.g. you can write "wire [7:0]
my_bus;", which is the same like "signal my_bus : std_logic_vector(7 downto
0);" in VHDL. And in VHDL you can define single bit signals, too, like int
"signal my_bit : std_logic;".

> what signals could have possibly meant and what I feel after reading
> about it is that,it is a source in an entity. ( if we are to extentd
> the concept of source to sink in VHDL )

No, it is more like a variable in computer programs. E.g. you can define a
state type like this:

type STATE_TYPE IS (IDLE, FOO, BAR);

Then you can use this type for a signal:

signal state : STATE_TYPE;

and in a process you can assign values to it and read from it:

process(reset, clk)
begin
if reset='1' then
state <= IDLE;
elsif rising_edge(clk) then
case state is
when IDLE =>
if something_interesting then
state <= FOO;
end if;
when FOO =>
if something_more_intersting then
state <= BAR;
end if;
when BAR =>
if unintersting then
state <= IDLE;
end if;
end case;
end if;
end process;

I think this is the same with "wire" in Verilog.

--
Frank Buss,
http://www.frank-buss.de, http://www.it4-systems.de

Actually in Verilog
you can never write on a wire

like

wire a;

initial
begin
a = 1;
#12
a<=1;
end


Does not work. it will not allow you to do so.
rather, you can have

reg b;
assign a= b;
where a is an wire.
Now when you do

initial
begin
b=1;
#1
=0;
end

THis will be a signal source for the wire a. So I am back to confusion

wrote:

> THis will be a signal source for the wire a. So I am back to confusion

One source of this confusion is that vhdl signals
(or verilog wires) are only strictly needed to wire up
entity/module instances in a structural design.

Signals/Wires are always required in a testbench
to hook up the UUT instance.

Here is a verilog synthesis module using no wires.

http://home.comcast.net/~mike_treseler/div10.v

Here are a few vhdl synthesis designs using no signals.

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

wrote:

> Actually in Verilog
> you can never write on a wire

I don't know much about Verilog, but looks like you are right and the
semantic is a bit different. E.g. in this example:

http://www.asic-world.com/tidbits/verilog_fsm.html

there is a function, which calculates the value of a wire. The result is
the same, if you use signals in VHDL with the syntax I've shown in my
previous posting, in Verilog it is just a bit more cumbersome to write,
because you can assign a value only once to a wire. Maybe Mike is right and
using registers in Verilog and variables in VHDL is better, because it
leads to smaller and better to maintain programs.

--
Frank Buss,
http://www.frank-buss.de, http://www.it4-systems.de

Dues UUT mean unit under test ( the same thing we call DUT , design
under test
-Parag

So the needs only comes in the Test bench scenario. What Mike meant
( if I read between the lines )

An UUT does not require any signals or wires ? Is it?
What about Verilog signals at the top level. Do they give you any
requirement for wire at all ( obviously the top level more often then
not is a test bench)
is the top level module synthesizable
-Parag