i can't simulate with modelsim XE III 6.2C

hello,

i wrote a simple vhdl program and i can simulate it. This is how i try it.

I have a simple vhdl progam written, i just added "c<= a and b" so i can do
some simulation.
A add a new source(test bench waveform) to my project.
(Notice: from now one my ise simulation toolbar is visible but the buttons
are disabled.)
I put my testsignals correct.
and now???

thanks, DaVidL

DaVidL

DaVidL wrote:

> A add a new source(test bench waveform) to my project.

Consider using a vhdl simulator.

http://groups.google.com/groups/sear...+inflexible%22

Mike Treseler

> Consider using a vhdl simulator.

You're wright. Thanks for the tip.

DaVidL