str to stdvec of converted values

Hello there,
I'm somewhat new to vhdl programming and am betting on there being more knowledgeable/smart people in this forum who could help. I’m trying to something similar to the thread below, whereby I’m having an input string fed in to be converted to a std_logic_vector of the converted values. I would be very appreciative and humbled if anybody could please help me out.
Thanks,
Jeff

http://www.velocityreviews.com/forum...gic-value.html

function str_to_stdvec(inp: string) return std_logic_vector is
variable temp: std_logic_vector((BLOCK_LENGTH+1)-1 downto 0) := (others => 'X');
begin
for i in inp'range loop
temp(i)<=std_logic'value(string(i) & NUL);
end loop;
return temp;
end;


Errors encountered:
# ** Error: TB_rev_A.vhd(53): Illegal type conversion from integer to string (numeric to array).
# ** Error: TB_rev_A.vhd(53): Target of signal assignment is not a signal.

J_R_L