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mn19
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      06-12-2007
Hi,

I'm searching for a VHDL implementation of a LFSR modulo 2 divisor to
calculate the remainder of a polynomial division, with one bit per
clock serial input and the remainder in output.

Can someone send me an example of the VHDL code?

Thank you.

 
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Mike Treseler
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      06-12-2007
mn19 wrote:

> I'm searching for a VHDL implementation of a LFSR modulo 2 divisor


http://groups.google.com/groups/search?q=vhdl+fcs
 
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