VHDL VGA controller

I've been working on a VGA controller on a DE2 for a while and I can't get the sync to work right. When I connect this to a monitor, the monitor says "out of range" meaning it's getting the signal, but the sync timing seems to be wrong. For the clock, I'm sending a 50 MHz clock through a PLL that brings it down to 25MHz and the resolution is 640 x 480. Can anyone recommend anything to fix it?


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

Entity VGA_ctrl IS
port( key: IN std_logic_vector(3 DOWNTO 0);
LEDR: OUT std_logic_vector(17 DOWNTO 0);
LEDG: OUT std_logic_vector(8 DOWNTO 0);
clock_50: IN std_logic;
VGA_R, VGA_G, VGA_B: OUT std_logic_vector(9 DOWNTO 0);
VGA_HS, VGA_VS, VGA_SYNC, VGA_CLK, VGA_BLANK: OUT std_logic;
pixel_row, pixel_column: OUT std_logic_vector(9 DOWNTO 0));
end vga_ctrl;

Architecture a of vga_ctrl is
signal horiz_sync, vert_sync, pixel_clock: std_logic;
signal video_on, video_on_v, video_on_h: std_logic;
signal h_count, v_count: std_logic_vector(9 DOWNTO 0);
signal clock: std_logic;
signal red, green, blue: std_logic_vector(9 DOWNTO 0);

constant h_pixels_across: Natural:=640;
constant h_sync_low: Natural:=664;
constant h_sync_high: Natural:=760;
constant h_end_count: Natural:=800;

constant v_pixels_down: Natural:=480;
constant v_sync_low: Natural:=491;
constant v_sync_high: Natural:=493;
constant v_end_count: Natural:=525;

COMPONENT video_PLL
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
end component;


Begin

video_pll_inst : video_pll PORT MAP (
inclk0 => clock_50,
c0 => clock
);

VGA_clk<= not clock;
VGA_SYNC<='1';
video_on<= (video_on_h and video_on_v);
vga_blank<= not video_on;


Process
Begin

Wait Until (clock'EVENT) and (clock='1');

If (h_count = h_end_count) Then
h_count <= "0000000000";
Else
h_count <= h_count+1;
End If;

If (v_count = v_end_count) and (h_count >= h_sync_low) Then
v_count <= "0000000000";
Elsif (h_count >= h_sync_low) then
v_count <= v_count+1;
End If;

If (h_count <= (H_sync_high)) and (h_count >= (H_sync_low)) Then
horiz_sync<='0';
Else
horiz_sync<='1';
End If;


If (v_count <= (V_sync_high)) and (v_count >= (v_sync_low)) Then
vert_sync<='0';
Else
vert_sync<='1';
End If;


If (h_count < h_pixels_across) Then
video_on_h<='1';
pixel_column<= h_count;
Else
video_on_h <= '0';
End If;


If (v_count <= v_pixels_down) Then
video_on_v<='1';
pixel_row<= V_count;
Else
video_on_v <='0';
End If;


VGA_HS <= horiz_sync;
VGA_VS <= vert_sync;

If video_on = '1' Then
red<="1111100100";
green<="1111100100";
blue<="1111100100";
Else
red<="0000000000";
green<="0000000000";
blue<="0000000000";
End If;

VGA_R<=red;
VGA_G<=green;
VGA_B<=blue;

End Process;
End a;

dashdingo

[quantum_dot]

I've been working on a VGA controller on a DE2 for a while and I can't get the sync to work right. When I connect this to a monitor, the monitor says "out of range" meaning it's getting the signal, but the sync timing seems to be wrong. For the clock, I'm sending a 50 MHz clock through a PLL that brings it down to 25MHz and the resolution is 640 x 480. Can anyone recommend anything to fix it?

Its difficult to find the cause of error by going through your source code. Have you tried to simulate it ? When the monitor says "out of range" does it refers to Vsync or Hsync ? It may be possible that the Vsync or Hsync is being counted wrong. But this can only be checked through simulation.

One more thing. I would suggest you to use DCM instead of PLL for generating clock freq. DCM can support a min of 25 MHz, so it should not be a problem.

quantum_dot

[jpk216]

Every time I have written a VGA driver it has always been 521 lines, not 524. That could be why you are getting the out of ranger error.

jpk216

[jpk216]

Instead of 525, sorry about that.

I know it is not a big issue at the moment but you may end up with timing issues later one. First, putting all of the code in a singe process with a wait statement at the beginning is a very bad coding practice. It will also give you trouble when you try and place and route it when the design gets larger. Also, since everything is in a sequential process the values do not update until the following clock cycle. That is what you normally want but in your case where you check the video_on signal, then assign the colors values, and then assign the colors to VGA_colors. It may look like everything works at first but you actually may be a column or two off.

jpk216