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VHDL - DCM clock signal output

 
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Old 06-11-2007, 07:31 PM   #1
Default DCM clock signal output


Hello again so because this group seems to have a lot of clever
guys in here i have a second question:

I use a DCM to rise the incoming frequency from 100 MHz to 200 MHz. I
used the wizard (XILINX CLOCKING WIZARD) and everything seems to work
fine. I need only the 200 MHz clock inside my program. Now someone
told me i cannot use a normal signal for the DCM output, because the
delay of a normal signal would be to slow and bring asynchronous
problems. In my opinion the synthesizer knows that this signal is a
clock-signal. Am i right or do i have to use a "special" signal?

Thanks and greets
Marc



TheThunder
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Old 06-12-2007, 06:52 PM   #2
Andy Peters
 
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Default Re: DCM clock signal output
On Jun 11, 11:31 am, TheThunder <marcal...@gmx.de> wrote:
> Hello again so because this group seems to have a lot of clever
> guys in here i have a second question:
>
> I use a DCM to rise the incoming frequency from 100 MHz to 200 MHz. I
> used the wizard (XILINX CLOCKING WIZARD) and everything seems to work
> fine. I need only the 200 MHz clock inside my program. Now someone
> told me i cannot use a normal signal for the DCM output, because the
> delay of a normal signal would be to slow and bring asynchronous
> problems. In my opinion the synthesizer knows that this signal is a
> clock-signal. Am i right or do i have to use a "special" signal?


If you used the clocking wizard, then the entity it creates
instantiates a BUFG on the relevant DCM outputs (which I presume in
your case was the CLK2X output). When you instantiate that entity,
you simply use the CLK2X signal output (whatever it's called) in your
design as the clock signal in all of your synchronous processes.

-a



Andy Peters
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