Synthesis of variable index array

Hello everyone,

I am new to VHDL and I am having problems with synthesis.

Is variable indexing of arrays (e.g. std_logic_vector) not really synthesizable?

For example,
-----
VARIABLE x : std_logic_vector(7 DOWNTO 0);
VARIABLE start : natural := 2;
VARIABLE end : natural := 4;
VARIABLE y : std_logic_vector(2 DOWNTO 0);
------
y := x(end DOWNTO start);

-------------------------------------------------

Why is this code not synthesizable? the tool I am using gives me
"Slice indices should be static"?

Is there someway to get around this in hardware?

The solution that I have till now is: Shifiting right and left till the part that we need remains and all others are 0's then ORing the parts that we need together.

Waiting for your replies.

Thank you very much
____
O.S.

oshouman

[Ahmed Samieh]

Originally Posted by oshouman

Why is this code not synthesizable? the tool I am using gives me
"Slice indices should be static"?

Is there someway to get around this in hardware?

the code is synthesizable, i'm using FPGA Advantage and xilinx ISE 9.1i

alias works too

ALIAS opcode : std_logic(3 DOWNTO 0) IS instruction(31 DOWNTO 28);

Ahmed Samieh

[quantum_dot]

Hello Oshouman,
Well the synthesis will definetly show problem with your code. The compiler looks for the defined boundaries while synthesizing the VHDL code. Giving a local variable or global variable parameter would result in error.

So, instead of defining "start" and "end" as variables, define them as constant and then compile.

constant start : natural := 2;
constant end : natural := 4;
VARIABLE x : std_logic_vector(7 DOWNTO 0);
VARIABLE y : std_logic_vector(2 DOWNTO 0);
------
y := x(end DOWNTO start);


Hope this will solve your problem

quantum_dot

[oshouman]

Dear Quantum_dot,

The idea is that I need to access a variable part (i.e. a slice of the vector) each time. In other words, the range changes each time the code executes.

Actually, I found a way to get around this, I do not really know if it is a stupid solution or a good one.

The idea is to have a separate function that copies a certain slice of a vector with start and end indeces to a target vector with different start and range indeces.

Here is the code (hint: I am new to VHDL and converting from programming):

FUNCTION copySliceN(input : std_logic_vector;
                       leftIndexInput, rightIndexInput : natural;
                       target : std_logic_vector;
                       leftIndexTarget, rightIndexTarget : natural)
    RETURN std_logic_vector IS
        VARIABLE inputSlice : std_logic_vector(target'left TO target'right) := (OTHERS => '0');
        VARIABLE conservedLeftPart : std_logic_vector(target'left TO target'right) := (OTHERS => '0');
        VARIABLE conservedRightPart : std_logic_vector(target'left TO target'right) := (OTHERS => '0');        
        VARIABLE output : std_logic_vector(target'left TO target'right) := (OTHERS => '0');
        BEGIN
            
            conservedLeftPart := SHR(target, conv_std_logic_vector(target'length-leftIndexTarget, 6));
            conservedLeftPart := SHL(conservedLeftPart, conv_std_logic_vector(target'length-leftIndexTarget, 6));
            
            conservedRightPart := SHL(target, conv_std_logic_vector(rightIndexTarget+1, 6));
            conservedRightPart := SHR(conservedRightPart, conv_std_logic_vector(rightIndexTarget+1, 6));

            inputSlice := conv_std_logic_vector(getSlice(input, leftIndexInput, rightIndexInput), target'length);
            inputSlice := SHL(inputSlice,
            conv_std_logic_vector(target'length-(rightIndexInput-leftIndexInput+1)-leftIndexTarget, target'length));
            
            output := or3(conservedLeftPart, conservedRightPart, inputSlice);
            
            RETURN output;
    END;

The function or3 just ORs three vectors.

When I use this functon, it does what I need and it is synthesizable.

Thanks for your reply and concern.

oshouman