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VHDL - Question on importing text from files |
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#1 |
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Hi I've been working on how to make my program manage to input 32 8-bit vectors in from one file (infile.txt) and write changed values into another file (outfile.txt). Here is the code that is relevant to file reading/writing:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library STD; use ieee.std_logic_textio.all; use std.textio.all; entity quickSorter is generic (infile : string := "infile.txt"; outfile : string := "outfile.txt"); end quickSorter; architecture Behavioral of quickSorter is begin controller : process variable tempData : std_logic_vector(7 downto 0); variable tempString : bit_vector(7 downto 0); variable sortArray : dataArray; variable fresult : file_open_status := status_error; variable tempLine : line; file in_fd : text open read_mode is infile; file out_fd : text open write_mode is outfile; begin --debug file processes file_open (fresult, in_fd, infile, read_mode); if (fresult /= OPEN_OK) then assert false report "usage: quickSort" severity failure; end if; file_open (fresult, out_fd, outfile, write_mode); if (fresult /= open_ok) then assert false report "usage: quickSort" severity failure; end if; --read file while (not endfile(in_fd)) loop readline (in_fd, tempLine); read (tempLine, tempString); end loop; --misc code --code which generates conditions for --the for loop underneath --write file for loop write (tempLine, tempString); writeLine (out_fd, tempLine); end loop; wait; end process; end Behavioral; The entire program compiles correctly, syntax-wise. However, the simulation always ends on the line after file_open (fresult, in_fd, infile, read_mode); which unfortunately means the file is incapable of being opened. I have added two user document source files to the project (infile.txt and outfile.txt). I have removed all code besides the relevant infile/outfile coding. Could someone please help me fix the error? Thanks for the assistance in advance. In case of reference, this is run with Xilinx software in vhdl code. boingboing |
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#2 |
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The file_open command is not needed. Check out the subtle changes I made to your code to see how this works now. You have to place all the incoming data into an array (sortArray) and then write it back out. Generate a counter (v_count) that will tell you how many you read in and how many are needed to write out.
Code:
scottcarl |
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