Hi all,

i'm tring to implement RC4 algorithm on fpga, i wrote the vhdl code

and simulation work fine too

but when i want to synthesize the errors and warnings pops up in my

face

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all;

--

ENTITY RC4 IS

GENERIC (d_width : natural := 8;

a_width : natural :=

;

PORT(clk : IN std_logic;

data_en : IN std_logic;

seed : IN std_logic_vector(63 DOWNTO 0) :=

X"0369CF258BE147AD";

data_out : OUT std_logic_vector(d_width-1 DOWNTO 0));

END ENTITY RC4;

--

ARCHITECTURE Arch OF RC4 IS

SUBTYPE byte IS natural RANGE 0 TO 2**d_width-1;

TYPE ram IS ARRAY (natural RANGE <>) OF byte;

SIGNAL x_s,y_s : byte;

SIGNAL rst_1_s,rst_2_s : std_logic := '0';

BEGIN

rise : PROCESS(clk,data_en,seed,rst_1_s,rst_2_s)

VARIABLE temp_1_v,temp_2_v,temp_3_v : byte;

VARIABLE state_v : ram(0 TO 2**a_width-1);

VARIABLE j_v,x_v,y_v : byte;

VARIABLE seed_v : ram(0 TO 7);

-- ATTRIBUTE logic_block : boolean;

-- ATTRIBUTE logic_block OF state_v: VARIABLE IS true;

BEGIN

IF (rst_1_s = rst_2_s) THEN

FOR i IN 7 DOWNTO 0 LOOP

seed_v(i) := to_integer( unsigned( seed((i+1)*8-1 DOWNTO

i*

) );

END LOOP;

FOR i IN 0 TO 2**a_width-1 LOOP

state_v(i) := i;

END LOOP;

FOR i IN 0 TO 2**a_width-1 LOOP

temp_1_v := seed_v(i mod

;

temp_2_v := state_v(i);

j_v := (temp_1_v + temp_2_v + j_v) mod 2**a_width;

temp_3_v := state_v(j_v);

state_v(i) := temp_3_v;

state_v(j_v) := temp_2_v;

END LOOP;

x_s <= 0;

y_s <= 0;

rst_1_s <= NOT(rst_2_s);

data_out <= (OTHERS => '0');

ELSIF rising_edge(clk) THEN

IF (data_en = '1') THEN

x_v := (x_s + 1) mod 2**a_width;

y_v := (y_s + state_v(x_v)) mod 2**a_width;

temp_1_v := state_v(x_v);

temp_2_v := state_v(y_v);

state_v(x_v) := temp_2_v;

state_v(y_v) := temp_1_v;

temp_3_v := state_v((temp_1_v + temp_2_v) mod 2**a_width);

data_out <= std_logic_vector(to_unsigned(temp_3_v, d_width));

x_s <= x_v;

y_s <= y_v;

END IF;

END IF;

END PROCESS rise;

new_frame_reset : PROCESS(data_en,rst_1_s)

BEGIN

IF rising_edge(data_en) THEN

rst_2_s <= rst_1_s;

END IF;

END PROCESS new_frame_reset;

END ARCHITECTURE Arch;

thanx,

Ahmed Samieh