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RC4 - someone help pleas!!

 
 
Ahmed Samieh
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      06-09-2007
Hi all,

i'm tring to implement RC4 algorithm on fpga, i wrote the vhdl code
and simulation work fine too
but when i want to synthesize the errors and warnings pops up in my
face

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--
ENTITY RC4 IS
GENERIC (d_width : natural := 8;
a_width : natural := ;
PORT(clk : IN std_logic;
data_en : IN std_logic;
seed : IN std_logic_vector(63 DOWNTO 0) :=
X"0369CF258BE147AD";
data_out : OUT std_logic_vector(d_width-1 DOWNTO 0));
END ENTITY RC4;
--
ARCHITECTURE Arch OF RC4 IS
SUBTYPE byte IS natural RANGE 0 TO 2**d_width-1;
TYPE ram IS ARRAY (natural RANGE <>) OF byte;
SIGNAL x_s,y_s : byte;
SIGNAL rst_1_s,rst_2_s : std_logic := '0';
BEGIN
rise : PROCESS(clk,data_en,seed,rst_1_s,rst_2_s)
VARIABLE temp_1_v,temp_2_v,temp_3_v : byte;
VARIABLE state_v : ram(0 TO 2**a_width-1);
VARIABLE j_v,x_v,y_v : byte;
VARIABLE seed_v : ram(0 TO 7);
-- ATTRIBUTE logic_block : boolean;
-- ATTRIBUTE logic_block OF state_v: VARIABLE IS true;
BEGIN
IF (rst_1_s = rst_2_s) THEN
FOR i IN 7 DOWNTO 0 LOOP
seed_v(i) := to_integer( unsigned( seed((i+1)*8-1 DOWNTO
i* ) );
END LOOP;
FOR i IN 0 TO 2**a_width-1 LOOP
state_v(i) := i;
END LOOP;
FOR i IN 0 TO 2**a_width-1 LOOP
temp_1_v := seed_v(i mod ;
temp_2_v := state_v(i);
j_v := (temp_1_v + temp_2_v + j_v) mod 2**a_width;
temp_3_v := state_v(j_v);
state_v(i) := temp_3_v;
state_v(j_v) := temp_2_v;
END LOOP;
x_s <= 0;
y_s <= 0;
rst_1_s <= NOT(rst_2_s);
data_out <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF (data_en = '1') THEN
x_v := (x_s + 1) mod 2**a_width;
y_v := (y_s + state_v(x_v)) mod 2**a_width;
temp_1_v := state_v(x_v);
temp_2_v := state_v(y_v);
state_v(x_v) := temp_2_v;
state_v(y_v) := temp_1_v;
temp_3_v := state_v((temp_1_v + temp_2_v) mod 2**a_width);
data_out <= std_logic_vector(to_unsigned(temp_3_v, d_width));
x_s <= x_v;
y_s <= y_v;
END IF;
END IF;
END PROCESS rise;
new_frame_reset : PROCESS(data_en,rst_1_s)
BEGIN
IF rising_edge(data_en) THEN
rst_2_s <= rst_1_s;
END IF;
END PROCESS new_frame_reset;
END ARCHITECTURE Arch;

thanx,

Ahmed Samieh

 
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Ahmed Samieh
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Posts: n/a
 
      06-10-2007
On Jun 9, 11:29 pm, Ahmed Samieh <(E-Mail Removed)> wrote:
> Hi all,


1st problem come from

> FOR i IN 0 TO 2**a_width-1 LOOP
> state_v(i) := i;
> END LOOP;


where state_v is 256*8 ram (array of 256 bytes)

but i don't understand why i got such a warning

Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
a_width => }, Net rst_1_s: This signal has multiple drivers. This
may lead to simulation mismatch.

???

any suggestions?

thanx,

Ahmed Samieh

 
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Michael Jørgensen
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      06-11-2007

"Ahmed Samieh" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> On Jun 9, 11:29 pm, Ahmed Samieh <(E-Mail Removed)> wrote:
>> Hi all,

>
> 1st problem come from
>
>> FOR i IN 0 TO 2**a_width-1 LOOP
>> state_v(i) := i;
>> END LOOP;

>
> where state_v is 256*8 ram (array of 256 bytes)
>
> but i don't understand why i got such a warning
>
> Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
> a_width => }, Net rst_1_s: This signal has multiple drivers. This
> may lead to simulation mismatch.


The warning is complaining about the signal rst_1_s. You are assigning to it
twice, and that leads to "multiple drivers".

-Michael.


 
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Ahmed Samieh
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Posts: n/a
 
      06-15-2007
On Jun 11, 2:00 pm, "Michael Jørgensen" <(E-Mail Removed)> wrote:
> "Ahmed Samieh" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed) oups.com...
>
>
>
>
>
> > On Jun 9, 11:29 pm, Ahmed Samieh <(E-Mail Removed)> wrote:
> >> Hi all,

>
> > 1st problem come from

>
> >> FOR i IN 0 TO 2**a_width-1 LOOP
> >> state_v(i) := i;
> >> END LOOP;

>
> > where state_v is 256*8 ram (array of 256 bytes)

>
> > but i don't understand why i got such a warning

>
> > Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
> > a_width => }, Net rst_1_s: This signal has multiple drivers. This
> > may lead to simulation mismatch.

>
> The warning is complaining about the signal rst_1_s. You are assigning to it
> twice, and that leads to "multiple drivers".
>
> -Michael.- Hide quoted text -
>
> - Show quoted text -


thanx Michael,

but if you talk a look in the code you will find only one driver for
rst_1_s
only
> rst_1_s <= NOT(rst_2_s);


so what is wrong with this code ?

Ahmed Samieh

 
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Brian Drummond
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      06-16-2007
On Fri, 15 Jun 2007 15:54:12 -0700, Ahmed Samieh <(E-Mail Removed)>
wrote:

>> > Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
>> > a_width => }, Net rst_1_s: This signal has multiple drivers. This
>> > may lead to simulation mismatch.

>>
>> The warning is complaining about the signal rst_1_s. You are assigning to it
>> twice, and that leads to "multiple drivers".


>thanx Michael,


>but if you talk a look in the code you will find only one driver for
>rst_1_s


>> rst_1_s <= NOT(rst_2_s);

and
SIGNAL rst_1_s,rst_2_s : std_logic := '0';

Make that two.

- Brian
 
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Ahmed Samieh
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Posts: n/a
 
      06-17-2007
On Jun 16, 4:22 pm, Brian Drummond <(E-Mail Removed)>
wrote:
> >> rst_1_s <= NOT(rst_2_s);

>
> and
> SIGNAL rst_1_s,rst_2_s : std_logic := '0';
>
> Make that two.
>
> - Brian


it is only an initial value to the signal not signal driver, so there
is no repot about rst_2_s

Ahmed Samieh

 
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Evan Lavelle
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      06-18-2007
On Sun, 17 Jun 2007 04:47:03 -0700, Ahmed Samieh <(E-Mail Removed)>
wrote:

>On Jun 16, 4:22 pm, Brian Drummond <(E-Mail Removed)>
>wrote:
>> >> rst_1_s <= NOT(rst_2_s);

>>
>> and
>> SIGNAL rst_1_s,rst_2_s : std_logic := '0';
>>
>> Make that two.
>>
>> - Brian

>
>it is only an initial value to the signal not signal driver, so there
>is no repot about rst_2_s


You're right, it's just a default value; this doesn't create a driver.
A signal always has a default value; you've just specified an explicit
one here, rather than using the 'implicit default' (in Verilog,
though, initialisation is just a shorthand for a continuous
assignment, so this *would* be a problem).

I think your problem is simply that your code is unsynthesisable, and
your tool is just trying (unsuccessfully) to tell you that. rst_1_s is
part of a combinatorial feedback loop (look at 'rst_1_s = rst_2_s' and
'rst_1_s <= not(rst_2_s'), *and* you're trying to give it a default
value. You need to sketch out what hardware you're trying to build,
and then try to code up that hardware, using some combination of
clocked and combinatorial processes.

Evan
 
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Evan Lavelle
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      06-18-2007
On Mon, 18 Jun 2007 09:57:18 +0100, Evan Lavelle <(E-Mail Removed)>
wrote:


>(in Verilog,
>though, initialisation is just a shorthand for a continuous
>assignment, so this *would* be a problem).


Technically, that should have been 'a blocking assignment in an
initial construct', rather than 'a continuous assignment'.

Evan
 
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Ahmed Samieh
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Posts: n/a
 
      06-18-2007
On Jun 18, 11:57 am, Evan Lavelle <(E-Mail Removed)> wrote:
> I think your problem is simply that your code is unsynthesisable, and
> your tool is just trying (unsuccessfully) to tell you that. rst_1_s is
> part of a combinatorial feedback loop (look at 'rst_1_s = rst_2_s' and
> 'rst_1_s <= not(rst_2_s'), *and* you're trying to give it a default
> value. You need to sketch out what hardware you're trying to build,
> and then try to code up that hardware, using some combination of
> clocked and combinatorial processes.
>
> Evan


thanx Evan,

ok..the problem in the code and the point which can't be done within
the code is :
i need to access 256 location using loop - only during one clock !!!

Ahmed Samieh

 
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Benjamin Todd
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      06-18-2007
Hey Ahmed,

I think you have several problems in your code. But I don't agree that
writing to 256 location in one cycle would be a problem, provided you don't
want a RAM. Obviously if you want to write to a RAM you need to do it line
by line etc.

Ok, to cut a long story short. The problem appears to come from two things:

firstly you make signals rst_1_s and rst_2_s and init them to '0'. be
cautious here, this won't simulate the same as it runs...

secondly, you've some crazy combinational logic with the two reset signals
and data_en. At the very least this _must_ make a latch for rst_1_s
somewhere.

Have a look at what you're trying to do, and (as others have already
suggested) try drawing out the circuit first by hand.

I also think you're cheating the simulator by including data_en in your
sensitivity list for 'rise' process.

to summarise:
-when data_en has a rising_edge state rst_2_s becomes the same as rst_1_s
-immediately these are equal, 'rise' executes and sets them inequal through
a combinational path.
-so you have a tiny ~ns pulse driving the first part of the 'rise' process
-BUT you have a clock AND data_en = '1' comparison also in the 'rise'
process ...

This is very confusing - how exactly are you trying to do this?? Have
another look through and post some more code when you make some progress

Ben


 
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