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how to use "wait" or dealy in a process?

 
 
Amit
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      06-09-2007
Hello group,

I need to simulate a dealy in a process. However I'm getting an error
as "A wait statement is illegal for a process with a sensitivity
list."

What should I do?

Regards.

 
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Amit
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      06-09-2007
On Jun 8, 10:03 pm, Amit <(E-Mail Removed)> wrote:
> Hello group,
>
> I need to simulate a dealy in a process. However I'm getting an error
> as "A wait statement is illegal for a process with a sensitivity
> list."
>
> What should I do?
>
> Regards.



Of course, I am having a sensitive list in my process since I'm using
FSM states. What I'm trying to do is creating a delay. Is it possible?

Thanks.

 
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JK
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      06-09-2007
On Jun 9, 10:10 am, Amit <(E-Mail Removed)> wrote:
> On Jun 8, 10:03 pm, Amit <(E-Mail Removed)> wrote:
>
> > Hello group,

>
> > I need to simulate a dealy in a process. However I'm getting an error
> > as "A wait statement is illegal for a process with a sensitivity
> > list."

>
> > What should I do?

>
> > Regards.

>
> Of course, I am having a sensitive list in my process since I'm using
> FSM states. What I'm trying to do is creating a delay. Is it possible?
>
> Thanks.


op <= ip after 10 ns;

 
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JK
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      06-09-2007
On Jun 9, 9:50 pm, JK <(E-Mail Removed)> wrote:
> op <= ip after 10 ns;- Hide quoted text -


This is for simulation purpose... It cant be synthesized.
Synthesizers ignore delay expressions('after'....)

Regards,
JK


 
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Amit
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      06-09-2007
On Jun 9, 11:18 am, JK <(E-Mail Removed)> wrote:
> On Jun 9, 9:50 pm, JK <(E-Mail Removed)> wrote:
>
> > op <= ip after 10 ns;- Hide quoted text -

>
> This is for simulation purpose... It cant be synthesized.
> Synthesizers ignore delay expressions('after'....)
>
> Regards,
> JK



JK,

Thanks indeed for your help.

 
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Pieter Hulshoff
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      06-11-2007
Amit wrote:
> I need to simulate a dealy in a process. However I'm getting an error
> as "A wait statement is illegal for a process with a sensitivity
> list."


A sensitive list is already considered a complete wait statement in itself, so
the VHDL language does not allow another wait statement. Remove your sensitivity
list, and add a WAIT ON <previous sensitivity list>; statement to the top of
your process.

Regards,

Pieter Hulshoff
 
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