"Sebastien Bourdeauducq" <(EMail Removed)> wrote in message
news:(EMail Removed) ups.com...
> Hi,
>
> I'd like to compute the arithmetic sum of a NATURAL signal and a
> STD_LOGIC_VECTOR signal, and store the value into a NATURAL signal,
> ie. a <= b + c, with a NATURAL, b NATURAL and c STD_LOGIC_VECTOR.
> How should I do ? Here the compiler complains about not finding a
> suitable definition of the + operator. I tried various combinations of
> TO_INTEGER(), TO_BIT_VECTOR(), UNSIGNED(), ... but no luck.
> The sum works when all operands are NATURAL.
The base VHDL language (through VHDL2002) does not define arithmetic on
std_logic_vectors. You have to use an external package (or write the
addition operator yourself) to get the desired functionality. Following the
IEEE standard approach, you will need to use package IEEE.numeric_std from
1076.31997. If IN1 and OUT1 are std_logic_vectors of the same length, and
IN2 is of type NATURAL, the following assignment works:
out1 <= std_logic_vector( unsigned(in1) + in2 );
This a) converts IN1 from SLV to UNSIGNED, b) performs the addition
creating an UNSIGNED result, and c) converts the result back to SLV.
Some alternative approaches:
Using Synopsys' package IEEE.std_logic_arith: out1 <= unsigned(in1) + in2;
Using Synopsys' package IEEE.std_logic_unsigned: out1 <= in1 + in2;
