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VHDL - generic check

 
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Old 06-08-2007, 11:59 AM   #1
Default generic check


how can a component perform a self-check on its generic map at
instanciation?

for example

entity mycomp is
generic(
param1 : integer := 1;
param2 : integer := 2);
.....
architecture...
....
begin...
....


let's say, I want to be sure that param2 is greater than param1 and
detect this assertion? "assert" does the job too late.


Stephane
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Old 06-08-2007, 02:08 PM   #2
Andy
 
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Default Re: generic check
On Jun 8, 5:59 am, Stephane <steph...@nospam.fr> wrote:
> how can a component perform a self-check on its generic map at
> instanciation?
>
> for example
>
> entity mycomp is
> generic(
> param1 : integer := 1;
> param2 : integer := 2);
> ....
> architecture...
> ...
> begin...
> ...
>
> let's say, I want to be sure that param2 is greater than param1 and
> detect this assertion? "assert" does the job too late.


Some tools (nc-sim) will try assertions on constant (including
generic) expressions during elaboration.

Most tools would trip out during compilation/elaboration if you had a
declaration that was out of bounds:

constant test_param1 : integer range 0 to param2 - 1 := param1;

Or more generally, maybe something like:

subtype test_t is boolean range true to true; -- is this legal?

constant test1: test_t := testfunc1(generic1);

Andy



Andy
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Old 06-08-2007, 03:23 PM   #3
Stephane
 
Posts: n/a
Default Re: generic check

> Some tools (nc-sim) will try assertions on constant (including
> generic) expressions during elaboration.
>
> Most tools would trip out during compilation/elaboration if you had a
> declaration that was out of bounds:
>
> constant test_param1 : integer range 0 to param2 - 1 := param1;
>
> Or more generally, maybe something like:
>
> subtype test_t is boolean range true to true; -- is this legal?


absolutely:

** Fatal: (vsim-3421) Value 0 is out of range 1 to 1.


thank you for your solution; it matches my need!

It is true that the problem would have appeared later at elaboration,
but it is far easier to have the line of an assertion to correct the bug
quickly.
Plus, the assertions at the beginning of architecture are almost part of
the specification...


Stephane
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Old 06-08-2007, 04:10 PM   #4
Amal
 
Posts: n/a
Default Re: generic check
On Jun 8, 10:23 am, Stephane <steph...@nospam.fr> wrote:
> > Some tools (nc-sim) will try assertions on constant (including
> > generic) expressions during elaboration.

>
> > Most tools would trip out during compilation/elaboration if you had a
> > declaration that was out of bounds:

>
> > constant test_param1 : integer range 0 to param2 - 1 := param1;

>
> > Or more generally, maybe something like:

>
> > subtype test_t is boolean range true to true; -- is this legal?

>
> absolutely:
>
> ** Fatal: (vsim-3421) Value 0 is out of range 1 to 1.
>
> thank you for your solution; it matches my need!
>
> It is true that the problem would have appeared later at elaboration,
> but it is far easier to have the line of an assertion to correct the bug
> quickly.
> Plus, the assertions at the beginning of architecture are almost part of
> the specification...


If the types do not match that can be caught by the simulator. Say if
you declare a positive parameter and assign 0 or negative to it,
elaboration would stop with an error.

One way to check for valid range, is to put assertions in your entity
declaration as follows:

entity mycomp is
generic(
param1 : integer := 1;
param2 : integer := 2
);
port (
);
-- -----------------------
-- translate_off
begin
assert( 1 < param1 and param1 < 5 )
report "param1 can should be in range [2..4]!"
severity ERROR;
-- translate_on
end entity mycomp;

architecture ??? of mycomp is
begin
end architecture ???;

Not that not all synthesis tools like to see begin before the entity
end statement. So, you need to put translate off/on pragmas around
it.

-- Amal



Amal
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