Connecting two bidirectional ports together

Hi,

Previously I heard that " it is impossible to connect two bidirectional port together in VHDL without any enable signals "
But tried like this,

Way 1

***********************************************
entity dec
CPU_I2C_SDA :inout std_logic;
I2C_SDA_MC :inout std_logic;

signal declared
signal enable1 : std_logic;
signal enable2 : std_logic;


Logic starts here..........

enable1 <= '1';
process(enable1)
begin
if enable1 ='1' then
CPU_I2C_SDA <= I2C_SDA_MC ;
else
CPU_I2C_SDA <= 'Z';
end if;
end process;

enable2 <= '1';
process(enable2)
begin
if enable2 ='1' then
I2C_SDA_MC <= CPU_I2C_SDA ;
else
I2C_SDA_MC <= 'Z';
end if;
end process;
***********************************************

Way 2:

***********************************************
process(I2C_SDA_MC )
begin
if I2C_SDA_MC = '0' then
CPU_I2C_SDA <= '0';
elsif I2C_SDA_MC = '1' then
CPU_I2C_SDA <= '1';
else
CPU_I2C_SDA <= 'Z';
end if;
end process;

process(CPU_I2C_SDA)
begin
if CPU_I2C_SDA = '0' then
I2C_SDA_MC <= '0';
elsif CPU_I2C_SDA = '1' then
I2C_SDA_MC <= '1';
else
I2C_SDA_MC <='Z';
end if;
end process;

********************************************

In this both logic, I got the ERROR during compilation.

Can anyone share why the error came ?

-V

VJN