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PC => FPGA, Parallel Port Communication

 
 
Rodrigo Ribeiro
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      06-05-2007
Hi,

Does anybody have an example of a bidirectional communication protocol
between the parallel port (EPP Mode) and the FPGA?

I need to work with digital image processing on the FPGA and need to
estabilish this communication to transfer data from the PC to be
processed on the FPGA.

I work with Quartus II Web Edition and a Altera Cyclone.


Thanks.

 
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Dave Higton
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      06-05-2007
In message <(E-Mail Removed) om>
Rodrigo Ribeiro <(E-Mail Removed)> wrote:

> Hi,
>
> Does anybody have an example of a bidirectional communication protocol
> between the parallel port (EPP Mode) and the FPGA?
>
> I need to work with digital image processing on the FPGA and need to
> estabilish this communication to transfer data from the PC to be
> processed on the FPGA.


Why on earth, in 2007, are you using a parallel port?

Dave
 
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Pascal Peyremorte
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      06-05-2007
Rodrigo Ribeiro a écrit :
> Hi,
>
> Does anybody have an example of a bidirectional communication protocol
> between the parallel port (EPP Mode) and the FPGA?
>
> I need to work with digital image processing on the FPGA and need to
> estabilish this communication to transfer data from the PC to be
> processed on the FPGA.


You would be better to use a fast transfer media like USB, ethernet, FireWire...

Pascal
 
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=?iso-8859-1?B?SGVybuFuIFPhbmNoZXo=?=
Guest
Posts: n/a
 
      06-08-2007
Hi

I'm using a XESS XS40 board that has parallel port communication with
the PC. For a little design that I made, I have a little example of
unidirectional communication (PC to FPGA Board). Maybe you can adapt
it or modify it to be bidirectional and improve it.

If you are interested, e-mail me.

Hernán Sánchez
hernan dot sanchez at iname dot com


On 5 jun, 07:11, Rodrigo Ribeiro <(E-Mail Removed)> wrote:
> Hi,
>
> Does anybody have an example of a bidirectional communication protocol
> between the parallel port (EPP Mode) and the FPGA?
>
> I need to work with digital image processing on the FPGA and need to
> estabilish this communication to transfer data from the PC to be
> processed on the FPGA.
>
> I work with Quartus II Web Edition and a Altera Cyclone.
>
> Thanks.



 
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