Mesa 5i21 Xilinx

Hi, I´m new to card using Xilinx chips. I´m developping a new vhd
prgogram, and on one Mesa example, at the very beginning of the code,
the following statements appear:

entity main is
port
(
-- bus interface signals --
LW_R: in std_logic;
DEN: in std_logic;
ADS: in std_logic;
BLAST: in std_logic;
WAITO: in std_logic;
READY: out std_logic;
INT: out std_logic;
HOLD: in std_logic;
HOLDA: inout std_logic;
RESET: in std_logic;
DISABLECONF: out std_logic;
DREQ: in std_logic;
DACK: in std_logic;
CCS: out std_logic;
INIT: out std_logic;

LAD: inout std_logic_vector (31 downto 0); -- data/address bus
lBE: in std_logic_vector (3 downto 0); -- byte enables

CHANDATA: inout std_logic_vector (31 downto 0);
RXEN: out std_logic_vector (15 downto 0);
TXEN: out std_logic_vector (15 downto 0);
LCLK: in std_logic;

-- led bits
LEDS: out std_logic_vector(7 downto 0)

);
end main;


CHANDATA refears to the I/O card signals, but I woul like to know what
are the others signals for. Are they internal signals, and no need of
manipulation is requiered?

thanks in advance,

Martin

Martin

On Jun 4, 6:46 pm, Martin <mrbia...@gmail.com> wrote:
> Hi, I´m new to card using Xilinx chips. I´m developping a new vhd
> prgogram, and on one Mesa example, at the very beginning of the code,
> the following statements appear:
>
> entity main is
> port
> (
> -- bus interface signals --
> LW_R: in std_logic;
> DEN: in std_logic;
> ADS: in std_logic;
> BLAST: in std_logic;
> WAITO: in std_logic;
> READY: out std_logic;
> INT: out std_logic;
> HOLD: in std_logic;
> HOLDA: inout std_logic;
> RESET: in std_logic;
> DISABLECONF: out std_logic;
> DREQ: in std_logic;
> DACK: in std_logic;
> CCS: out std_logic;
> INIT: out std_logic;
>
> LAD: inout std_logic_vector (31 downto 0); -- data/address bus
> lBE: in std_logic_vector (3 downto 0); -- byte enables
>
> CHANDATA: inout std_logic_vector (31 downto 0);
> RXEN: out std_logic_vector (15 downto 0);
> TXEN: out std_logic_vector (15 downto 0);
> LCLK: in std_logic;
>
> -- led bits
> LEDS: out std_logic_vector(7 downto 0)
>
> );
> end main;
>
> CHANDATA refers to the I/O card signals, but I would like to know what
> are the others signals for. Are they internal signals, and no need of
> manipulation is required?
>
> thanks in advance,
>
> Martin

No offense, but, your question indicates that you are just learning
VHDL.

This should help: <http://www.amazon.com/gp/product/
1558605207/103-4357423-2097418>

ghelbig@lycos.com