tasks in differenet rising edges.

Hello Group,

Would you please tell me how can I implement the following steps in
VDHL code?

1) At one rising edge of clock, check input1
2) On the next edge, assign a value a to output1
3) At the thrid rising edge, a consumer must get data[]

What I don't know is how can I do one task during 1st rising edge, 2nd
task during 2nd rising edge and a 3rd task during the thrid rising
edge of clock.

thanks
amit

Amit

On Sun, 03 Jun 2007 13:17:42 -0700, Amit <> wrote:

>
>Hello Group,
>
>Would you please tell me how can I implement the following steps in
>VDHL code?
>
>1) At one rising edge of clock, check input1
>2) On the next edge, assign a value a to output1
>3) At the thrid rising edge, a consumer must get data[]
>
>What I don't know is how can I do one task during 1st rising edge, 2nd
>task during 2nd rising edge and a 3rd task during the thrid rising
>edge of clock.

STATE MACHINE.

At least, that's if you want to write VHDL that represents a piece
of hardware. It sounds like that's what you want to do.

Oh, and a non-meaningless specification would be good too.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

On Jun 3, 11:17 pm, Amit <amit.ko...@gmail.com> wrote:
> Hello Group,
>
> Would you please tell me how can I implement the following steps in
> VDHL code?
>
> 1) At one rising edge of clock, check input1
> 2) On the next edge, assign a value a to output1
> 3) At the thrid rising edge, a consumer must get data[]
>
> What I don't know is how can I do one task during 1st rising edge, 2nd
> task during 2nd rising edge and a 3rd task during the thrid rising
> edge of clock.
>
> thanks
> amit

use FSM,

S1 : read input, set S2
S2 : assing a to output, set S3
S3 : blablabla (anything), set S1

Ahmed Samieh

Ahmed Samieh