help with a problem compiling

hi, i had found these errors in modelsim (in xilinx i don't have problems compiling):

** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(100): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(105): Statement cannot be labeled.
-- Loading entity a_not2
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(123): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(127): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(134): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(137): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(139): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(141): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(143): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(145): Statement cannot be labeled.
** Error: C:/digitales2/reloj_intento/color_camino_dat.vhd(213): VHDL Compiler exiting


------------------------------------------------
here is color_camino_dat.vhd
note: the packages used in this entity don't show errors, and others files that use same packages don't show these errors.
-------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.pack_mux.all;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity color_camino_dat is
Port (-- modo:in std_logic_vector(1 downto 0);


load : in std_logic_vector(5 downto 0);
sel : in std_logic_vector(13 downto 0);
clk : in std_logic;
reset : in std_logic;
-- col_horaut std_logic_vector(2 downto 0);
col_minut std_logic_vector(2 downto 0);
col_segut std_logic_vector(2 downto 0);
col_diaut std_logic_vector(2 downto 0);
col_fechaut std_logic_vector(2 downto 0);
col_aput std_logic_vector(2 downto 0);
col_horaut std_logic_vector(2 downto 0);
min0_a: in std_logic_vector(3 downto 0);
min1_a: in std_logic_vector(3 downto 0);
hora_a: in std_logic_vector(3 downto 0);
hora1_a: in std_logic_vector(3 downto 0);
apm_a:in std_logic;

hora_cron: in std_logic_vector(3 downto 0);
hora1_cron: in std_logic_vector(3 downto 0);
min0_cron: in std_logic_vector(3 downto 0);
min1_cron: in std_logic_vector(3 downto 0);

seg0_r: in std_logic_vector(3 downto 0);
seg1_r: in std_logic_vector(3 downto 0);

seg0_cron: in std_logic_vector(3 downto 0);
seg1_cron: in std_logic_vector(3 downto 0);

dec: in std_logic_vector(3 downto 0);
dia_s: in std_logic_vector(3 downto 0);

ano0 : in std_logic_vector(3 downto 0);
ano1 : in std_logic_vector(3 downto 0);

min0_r: in std_logic_vector(3 downto 0);
min1_r: in std_logic_vector(3 downto 0);
hora_r: in std_logic_vector(3 downto 0);
hora1_r: in std_logic_vector(3 downto 0);
apm_r:in std_logic;

min0_c: out std_logic_vector(3 downto 0);
min1_c: out std_logic_vector(3 downto 0);
hora_c: out std_logic_vector(3 downto 0);
hora1_c: out std_logic_vector(3 downto 0);
seg0_c: out std_logic_vector(3 downto 0);
seg1_c: out std_logic_vector(3 downto 0);
dia_c: out std_logic_vector(3 downto 0);
apm_cut std_logic
);

end color_camino_dat;

architecture Behavioral of color_camino_dat is


signal min,seg,dia,fecha,ap,hora,not_min,not_seg,not_dia, not_fecha,not_ap,not_hora : std_logic_vector(2 downto 0);

signal mux1,mux2,mux3,mux4,mux0,mux5 : std_logic_vector(2 downto 0);



begin

col_seg<=seg;
col_min<=min;
col_dia<=dia;
col_fecha<=fecha;
col_ap<=ap;
col_hora<=hora;


mux_seg00: mux generic map(b=>3)
port map(i1 =>seg0_r,i2 =>seg0_cron, s=>sel(13), f=>seg0_c);

mux_seg1:mux generic map(b=>3)
port map(i1 =>seg1_r,i2 =>seg1_cron, s=>sel(13), f=>seg1_c);

mux_dia:mux generic map(b=>3)
port map(i1 =>dia_s,i2 =>dec, s=>sel(12), f=>dia_c);

mux_min0:mux4 generic map(b=>3)
Port map ( i0 =>min0_r, i1 =>min0_a,i2 =>ano0, i3 =>min0_cron, s =>sel(13 downto 12), f =>min0_c);

mux_min1:mux4 generic map(b=>3)
Port map ( i0 =>min1_r, i1 =>min1_a,i2 =>ano1, i3 =>min1_cron, s =>sel(13 downto 12), f =>min1_c);



not_4:a_not2 port map(a=>min,a_not=>not_min);

not_3:a_not2 port map(a=>seg,a_not=>not_seg);

not_2:a_not2 port map(a=>dia,a_not=>not_dia);

not_1:a_not2 port map(a=>fecha,a_not=>not_fecha);

not_0:a_not2 port map(a=>ap,a_not=>not_ap);

not_5:a_not2 port map(a=>hora,a_not=>not_hora);


mux_ap:mux1
port map(i1 =>apm_r,i2 =>apm_a, s=>sel(12), f=>apm_c);



mux_hora: mux3
Port map (s=>sel(13 downto 12),i1=>hora_r,i2 =>hora_a,i3 =>hora_cron,f =>hora_c);


mux_hora1: mux3
Port map (s=>sel(13 downto 12),i1=>hora1_r,i2 =>hora1_a,i3 =>hora1_cron,f =>hora1_c);





mux2_ap:mux2
port map (i1=>not_ap,s=>sel(1 downto 0),f=>mux0);

mux_col_seg : mux2 port map (i1=>not_seg,s=>sel(3 downto 2),f=>mux1);

mux_color_min : mux2 port map (i1=>not_min,s=>sel(5 downto 4),f=>mux2);

mux2_hora:mux2 port map (i1=>not_hora,s=>sel(7 downto 6),f=>mux3);

mux2_dia:mux2 port map (i1=>not_dia,s=>sel(9 downto ,f=>mux4);

mux2_fecha:mux2 port map (i1=>not_fecha,s=>sel(11 downto 10),f=>mux5);


process(clk,reset) begin
if reset='1' then
ap<=(others=>'0');
elsif clk'event and clk='1' then
if load(0)='1' then
ap<=mux0;
else null; end if;
end if;
end process;




process(clk,reset) begin
if reset='1' then
seg<=(others=>'0');
elsif clk'event and clk='1' then
if load(1)='1' then
seg<=mux1;
else null; end if;
end if;
end process;

process(clk,reset) begin
if reset='1' then
min<=(others=>'0');
elsif clk'event and clk='1' then
if load(2)='1' then
min<=mux2;
else null; end if;
end if;
end process;

process(clk,reset) begin
if reset='1' then
hora<=(others=>'0');
elsif clk'event and clk='1' then
if load(3)='1' then
hora<=mux3;
else null; end if;

end if;
end process;

process(clk,reset) begin
if reset='1' then
dia<=(others=>'0');
elsif clk'event and clk='1' then
if load(4)='1' then
dia<=mux4;
else null; end if;
end if;
end process;


process(clk,reset) begin
if reset='1' then
fecha<=(others=>'0');
elsif clk'event and clk='1' then
if load(5)='1' then
fecha<=mux5;
else null; end if;
end if;
end process;

end Behavioral;

carlobar