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Simulation of VHDL in xilinx from a C program?

 
 
jesse lackey
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      05-25-2007
My apologies if this is posted twice. The first one doesn't seem to
have made it out.

I'd like to be able to drive the simulator in ISE from a C program. I'm
using Windows. Ideally, it would be a command-line C app I'd make in VC++.

I have no idea if this is possible and looking around xilinx.com and
google searches aren't turning much up.

Large-scale designs must be tested this way; or so I think. Writing the
testbench in VHDL would be a much bigger effort than in C, and I'd like
to have the option anyway of doing it as a full Windows app with a gui
to do a bunch of things. So the C program would set a bunch of inputs,
drive a clock, watch the outputs.

Now I figure as an alternative I could use C to generate a file of test
vectors, and then have a VHDL testbench read this file, run the
simulation, and write an output file. The C code could then check the
output file. I'd rather not have it be this kludgey if possible.

Any advice?

Thanks!
Jesse
 
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HT-Lab
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      05-25-2007

"jesse lackey" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> My apologies if this is posted twice. The first one doesn't seem to have
> made it out.
>
> I'd like to be able to drive the simulator in ISE from a C program. I'm
> using Windows. Ideally, it would be a command-line C app I'd make in
> VC++.
>
> I have no idea if this is possible and looking around xilinx.com and
> google searches aren't turning much up.
>
> Large-scale designs must be tested this way; or so I think. Writing the
> testbench in VHDL would be a much bigger effort than in C, and I'd like to
> have the option anyway of doing it as a full Windows app with a gui to do
> a bunch of things. So the C program would set a bunch of inputs, drive a
> clock, watch the outputs.
>
> Now I figure as an alternative I could use C to generate a file of test
> vectors, and then have a VHDL testbench read this file, run the
> simulation, and write an output file. The C code could then check the
> output file. I'd rather not have it be this kludgey if possible.
>
> Any advice?
>
> Thanks!
> Jesse


I am not sure about the ISE simulator but perhaps you can get hold of the
Xilinx Modelsim OEM version? In that case you can use Tcl to provide the
stimulus (look up force/when/examine Tcl commands to name a few) and use
sockets (same as a file in Tcl) to communicate with your C program.

If you need speed than Tcl might not be the best solution, in that case you
need to spend some money and either get Modelsim PE+SystemC, Modelsim
SE+FLI or ActiveHDL+VHPI to provide a thin interface layer to your C
program.

Hans
www.ht-lab.com




 
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Paul Uiterlinden
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      05-25-2007
jesse lackey wrote:

> Now I figure as an alternative I could use C to generate a file of test
> vectors, and then have a VHDL testbench read this file, run the
> simulation, and write an output file. The C code could then check the
> output file. I'd rather not have it be this kludgey if possible.


The main disadvantage of this method is that you cannot write models that
react on the outputs of your device under verification. A simple example is
a processor model that must wait on an acknowledge before continuing a
current bus cycle. So I definitely would not would go down this path.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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GŁnther Jehle
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      05-25-2007
> Any advice?

Look at ghdl ( http://ghdl.free.fr). It is a VHDL Simulator using a compiler
to produces an executable to simulate. The used compiler is the well known
gcc. Since it is a compiler, you can link it with your own c functions. See
an example at http://ghdl.free.fr/vhpidirect/ or read the manual.

hth
GŁnther Jehle



 
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