Hallo over again,

maybe you don't understanded my question...

So, i try to explain again, and then maybe you can same suggest.

Convolution compound of multiplication and addition. So, in VHDL i use just adders. For each pixels of the image (800x600 pixels) after multiplication and addtion operations i need most 25 bits adder. () as 25 bist adder compose of 294 logic gates, convolution operation need 138.240.006 gates (295x800x600).

All intermediate counts i can save in the memory. It's goot thought?

For examle:

1111 x 1111:

+ 1111

+ 11110

+ 111100

1111000

------

11100001
For every addition operation (the are 3) intermediate results i save in memory (1111+11110=

**101101**)

**101101** i save, then i take

**101101** and add with 111100 and so on. Like inputs ant outputs for 25 bits adder i just use adders of memory.

I could use more adders (without saving all intermediate operation), but FPGA have not enough of logic cells.

For this project i plan ahead use this FPGA Board:

http://www.xilinx.com/xlnx/xebiz/des...V5-ML505-UNI-G