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[krishlal925]

i got that error on the line after begin check it out:


signal C : std_logic_vector(3 downto 0);

begin
halfadder port map(A(0), B(0), S(0), c => C(0));
fulladder port map(A(1), B(1), C(0), S(1), Cout => C(1));
fulladder port map(A(2), B(2), C(1), S(2), Cout => C(2));
fulladder port map(A(3), B(3), C(2), S(3), Cout => Cout);
end Behavioral;

any suggestions?

[jaga]

can u please define A B C an all...

[joris]

you must add a label to each instance, like:

begin
ha: halfadder port map(A(0), B(0), S(0), c => C(0));
fa1: fulladder port map(A(1), B(1), C(0), S(1), Cout => C(1));
fa2: fulladder port map(A(2), B(2), C(1), S(2), Cout => C(2));
fa3: fulladder port map(A(3), B(3), C(2), S(3), Cout => Cout);
end Behavioral;