Velocity Reviews > VHDL > quwstion from newbie

# quwstion from newbie

mobi999
Junior Member
Join Date: May 2007
Posts: 2

 05-21-2007
Hi!
can u explain what this line do

result <= ('0' & A)+('0' & B);

esp this '0' thing

thanks

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------

generic(n: natural :=2);
port( A: in std_logic_vector(n-1 downto 0);
B: in std_logic_vector(n-1 downto 0);
carry: out std_logic;
sum: out std_logic_vector(n-1 downto 0)
);

--------------------------------------------------------

-- define a temparary signal to store the result

signal result: std_logic_vector(n downto 0);

begin

-- the 3rd bit should be carry

result <= ('0' & A)+('0' & B);
sum <= result(n-1 downto 0);
carry <= result(n);

end behv;

Paxwell
Junior Member
Join Date: May 2007
Posts: 2

 05-22-2007
Since the answer is one bit more than the inputs. If the '0' wouldn&#180;t be there the carry would be lost. You can&#180;t add two vectors of size x and get a result of size x+1. So the two input vectors have to extended with the most significant bit.
The vectors are unsigned, that&#180;s important. If a and b are signed it should be a(MSB) & a + b(MSB) & b.

I hope this explains some.

Last edited by Paxwell; 05-22-2007 at 01:15 PM..