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Need to delay a signal a great number of clk cycles

martin.wahlstedt martin.wahlstedt is offline
Junior Member
Join Date: Mar 2007
Posts: 14

Do someone have any tricks on how to delay a signal without using shift registers? Need to delay an enable signal (one bit) approx. 1024 clock cycles, and an shift register implementation will be quite big. The implementation is to be synthesises so 'after' commands are not possible.

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scottcarl scottcarl is offline
Join Date: May 2007
Location: USA
Posts: 51
Use a 10-bit counter to delay something 1024 clock cycles. Use this 2-state state machine.

Count_grab : process(clk, reset)
  if (reset = '1') then
    counter               <= (others => '0'); -- Counts from 0 to 1023
    YOUR_END_PULSE <= '0';  
    s_pulse_grab <= s_idle;
  elsif elsif rising_edge(clk) then
       counter              <= (others => '0'); -- defualt wherever it's not defined
       YOUR_END_PULSE <= '0';   -- defualt wherever it's not defined
    when s_idle => 
      if (incoming_pulse = '1') then  -- Latch in the incoming pulse 
        counter        <= counter + '1'; -- Start counting
        s_pulse_grab <= s_enabling;
        s_pulse_grab <= s_idle;
      end if;
    when s_enabling => 
      if (counter = 1022) then  -- Find one sample before the end 
        YOUR_END_PULSE <= '1';   -- This is your 1024 delayed pulse
        s_pulse_grab       <= s_idle;
        counter              <= counter + '1'; 
        s_pulse_grab       <= s_enabling;
      end if;
    when others =>
  end if;
end process;

Last edited by scottcarl; 05-15-2007 at 09:26 PM..
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