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dual-edge sensitivity

 
 
travislagrone travislagrone is offline
Junior Member
Join Date: May 2007
Posts: 1
 
      05-10-2007
I'm trying to use both edges of my clock signal to count for a clock divider using VHDL. Behaviorally, the simulation works, but it won't synthesize. I'm using a Xilinx Spartan-3e FPGA. I tried it in Verilog and I'm getting the same results. Is this something that VHDL is not allowing me to do or is it my FPGA? Here's an example:


----------------------------------------------------------------------
count : process (clk)
begin

if ( rising_edge(clk) or falling_edge(clk) )then
if num = 20 then
new_clk <= not new_clk;
num <= 0;
else
num <= num + 1;
end if;
clk_slow <= new_clk;
end if;
end process count;
---------------------------------------------------------------------


this didn't work.. so I tried this:


---------------------------------------------------------------------
count : process (clk)
begin

if rising_edge(clk) then
if num = 0 then
new_clk <= not new_clk;
num <= 0;
else
num <= num + 1;
end if;
elsif falling_edge(clk) then
if num = 0 then
new_clk <= not new_clk;
num <= 0;
else
num <= num + 1;
end if;
end if;
clk_slow <= new_clk;
end process count;
---------------------------------------------------------------------

And that gave me errors because of the way I'm synchronizing my signal "num". Any ideas?

Travis
 
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Paxwell Paxwell is offline
Junior Member
Join Date: May 2007
Posts: 2
 
      05-22-2007
You are trying to clock a flip flop on both edges, I don´t think that is possible with any Xilinx FPGA.
Spartan 3 has a DCM (Digital Clock Manager) that can divide the clock for you. Search the home page for application notes.
 
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scottcarl scottcarl is offline
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Join Date: May 2007
Location: USA
Posts: 51
 
      05-22-2007
You can never use both edges of a clock in the same process for a synthesizable design. You must create 2 seperate processes with one using a rising_edge and the other the falling_edge. I'm not sure why you would ever need to count both edges since if you count one you essentially double it to indicate that you have counted both. You might want to explain a little better what you're tying to accomplish.

It is possible to use the high & low levels of the clock to possibly mux different data onto the same line to double throughput speeds. I would recommend simply doubling the clock speed in this case though for a more precise design.

Scott
 

Last edited by scottcarl; 05-22-2007 at 03:52 PM..
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