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What is the difference between 'std_logic_vecotor' and 'signed'

 
 
Zhi
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      05-07-2007


eg: a : std_logic_vector(3 downto 0) ;

if a < "0111" then
a :=a+"0001";
WRITE (buf_in,doutb);
WRITELINE(to_text,buf_in);
else
report "error";

I found when a ="1000", "1001","1010"... It never report "error".

I guess does it take the first left bit as 'sign'. If it is so, what
the difference between std_logic_vector and signed. And if I only want
to write 8 value to to_text. How to give the restriction.

Thanks.

 
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Brad Smallridge
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      05-07-2007
Try this:
signal a : std_logic_vector(3 downto 0);
and this:
a <= a+"0001";

Brad Smallridge
Ai Vision


"Zhi" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) ups.com...
>
>
> eg: a : std_logic_vector(3 downto 0) ;
>
> if a < "0111" then
> a :=a+"0001";
> WRITE (buf_in,doutb);
> WRITELINE(to_text,buf_in);
> else
> report "error";
>
> I found when a ="1000", "1001","1010"... It never report "error".
>
> I guess does it take the first left bit as 'sign'. If it is so, what
> the difference between std_logic_vector and signed. And if I only want
> to write 8 value to to_text. How to give the restriction.
>
> Thanks.
>



 
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Zhi
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Posts: n/a
 
      05-07-2007
On 7 May, 18:00, "Brad Smallridge" <(E-Mail Removed)>
wrote:
> Try this:
> signal a : std_logic_vector(3 downto 0);
> and this:
> a <= a+"0001";
>
> Brad Smallridge
> Ai Vision
>
> "Zhi" <(E-Mail Removed)> wrote in message
>
> news:(E-Mail Removed) ups.com...
>
>
>
>
>
> > eg: a : std_logic_vector(3 downto 0) ;

>
> > if a < "0111" then
> > a :=a+"0001";
> > WRITE (buf_in,doutb);
> > WRITELINE(to_text,buf_in);
> > else
> > report "error";

>
> > I found when a ="1000", "1001","1010"... It never report "error".

>
> > I guess does it take the first left bit as 'sign'. If it is so, what
> > the difference between std_logic_vector and signed. And if I only want
> > to write 8 value to to_text. How to give the restriction.

>
> > Thanks.- Hide quoted text -

>
> - Show quoted text -


Thanks Brad. But it doesn't work. I guess it is the library problem
again. When I change ieee. std_logic_signed to std_logic_unsigned.
Everything works. I have read some posters to recommend to use
numeric_std instead of std_logic_signed/unsigned. I have not have much
experience on it before. This time ieee.std libraries got me mad.

 
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Brad Smallridge
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Posts: n/a
 
      05-07-2007
> Thanks Brad. But it doesn't work. I guess it is the library problem
> again. When I change ieee. std_logic_signed to std_logic_unsigned.
> Everything works. I have read some posters to recommend to use
> numeric_std instead of std_logic_signed/unsigned. I have not have much
> experience on it before. This time ieee.std libraries got me mad.


Yes. I have been told that with numeric_std you can have both signed
and unsigned signals in the same module, and that the names of the
conversion functions are more understandable. I usually use the
unsigned library by Xilinx default.

Brad Smallridge
AiVision


 
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Zhi
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Posts: n/a
 
      05-07-2007
On 7 May, 19:04, "Brad Smallridge" <(E-Mail Removed)>
wrote:
> > Thanks Brad. But it doesn't work. I guess it is the library problem
> > again. When I change ieee. std_logic_signed to std_logic_unsigned.
> > Everything works. I have read some posters to recommend to use
> > numeric_std instead of std_logic_signed/unsigned. I have not have much
> > experience on it before. This time ieee.std libraries got me mad.

>
> Yes. I have been told that with numeric_std you can have both signed
> and unsigned signals in the same module, and that the names of the
> conversion functions are more understandable. I usually use the
> unsigned library by Xilinx default.
>
> Brad Smallridge
> AiVision


Yeah, I have been told to use numeric_std library as well. But I use
some RAM in my project. The interface port is std_logic_vector. I
have to do the '+' operations in the codes and NUMERIC_STD doesn't
support 'slv' '+'/'-' operation. Then I choose to use Library
std_logic_signed. One more thing, if I choose use library
std_logic_unsigned, what does it consider my 'signed' type value in my
codes? Actually when I compared the STD_LOGIC_SIGNED and
STD_LOGIC_UNISGNED packages. i did not see the difference.

 
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Jim Lewis
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      05-07-2007
Zhi
Go read my paper, "VHDL Math Tricks of the Trade", from
MAPLD 2003 which is posted at:
http://www.synthworks.com/papers/index.htm

Cheers,
Jim

> On 7 May, 19:04, "Brad Smallridge" <(E-Mail Removed)>
> wrote:
>>> Thanks Brad. But it doesn't work. I guess it is the library problem
>>> again. When I change ieee. std_logic_signed to std_logic_unsigned.
>>> Everything works. I have read some posters to recommend to use
>>> numeric_std instead of std_logic_signed/unsigned. I have not have much
>>> experience on it before. This time ieee.std libraries got me mad.

>> Yes. I have been told that with numeric_std you can have both signed
>> and unsigned signals in the same module, and that the names of the
>> conversion functions are more understandable. I usually use the
>> unsigned library by Xilinx default.
>>
>> Brad Smallridge
>> AiVision

>
> Yeah, I have been told to use numeric_std library as well. But I use
> some RAM in my project. The interface port is std_logic_vector. I
> have to do the '+' operations in the codes and NUMERIC_STD doesn't
> support 'slv' '+'/'-' operation. Then I choose to use Library
> std_logic_signed. One more thing, if I choose use library
> std_logic_unsigned, what does it consider my 'signed' type value in my
> codes? Actually when I compared the STD_LOGIC_SIGNED and
> STD_LOGIC_UNISGNED packages. i did not see the difference.
>

 
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Andy
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Posts: n/a
 
      05-07-2007
On May 7, 2:13 pm, Zhi <(E-Mail Removed)> wrote:
> On 7 May, 19:04, "Brad Smallridge" <(E-Mail Removed)>
> wrote:
>
> > > Thanks Brad. But it doesn't work. I guess it is the library problem
> > > again. When I change ieee. std_logic_signed to std_logic_unsigned.
> > > Everything works. I have read some posters to recommend to use
> > > numeric_std instead of std_logic_signed/unsigned. I have not have much
> > > experience on it before. This time ieee.std libraries got me mad.

>
> > Yes. I have been told that with numeric_std you can have both signed
> > and unsigned signals in the same module, and that the names of the
> > conversion functions are more understandable. I usually use the
> > unsigned library by Xilinx default.

>
> > Brad Smallridge
> > AiVision

>
> Yeah, I have been told to use numeric_std library as well. But I use
> some RAM in my project. The interface port is std_logic_vector. I
> have to do the '+' operations in the codes and NUMERIC_STD doesn't
> support 'slv' '+'/'-' operation. Then I choose to use Library
> std_logic_signed. One more thing, if I choose use library
> std_logic_unsigned, what does it consider my 'signed' type value in my
> codes? Actually when I compared the STD_LOGIC_SIGNED and
> STD_LOGIC_UNISGNED packages. i did not see the difference.


Use numeric_std!!!

subtype slv is std_logic_vector; -- abbreviation
signal address is slv(...);
....
address <= slv(unsigned(address) + 1);

Or infer your memory from an array, and use an integer for the address
(index of the array).

The only difference between std_logic_signed and std_logic_unsigned is
the behavior of the operands. Those in ...signed interpret their slv
arguments as signed quantities, and those in ...unsigned interpret
theirs as unsigned quantities.

Andy

 
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Mike Treseler
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Posts: n/a
 
      05-07-2007
Zhi wrote:

> NUMERIC_STD doesn't
> support 'slv' '+'/'-' operation.


Of course it doesn't.
Std_logic_vector could be signed, unsigned or neither.
Use the type you really want internally.
Cast to std_logic_vector for port outputs if need be.

> One more thing, if I choose use library
> std_logic_unsigned, what does it consider my 'signed' type value in my
> codes?


That's the problem.
Std_logic_unsigned is poorly named.
It only knows about boolean and Std_logic_vector.

Actually when I compared the STD_LOGIC_SIGNED and
> STD_LOGIC_UNISGNED packages. i did not see the difference.


That's why the packages fail
if I want to do both signed
and unsigned math.


-- Mike Treseler
 
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Zhi
Guest
Posts: n/a
 
      05-08-2007
Thanks all your guys.

Mike Treseler wrote:
> Zhi wrote:
>
> > NUMERIC_STD doesn't
> > support 'slv' '+'/'-' operation.

>
> Of course it doesn't.
> Std_logic_vector could be signed, unsigned or neither.
> Use the type you really want internally.
> Cast to std_logic_vector for port outputs if need be.
>
> > One more thing, if I choose use library
> > std_logic_unsigned, what does it consider my 'signed' type value in my
> > codes?

>
> That's the problem.
> Std_logic_unsigned is poorly named.
> It only knows about boolean and Std_logic_vector.
>
> Actually when I compared the STD_LOGIC_SIGNED and
> > STD_LOGIC_UNISGNED packages. i did not see the difference.

>
> That's why the packages fail
> if I want to do both signed
> and unsigned math.
>
>
> -- Mike Treseler


 
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