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Hi,

I am trying to build a edge detector circuit. I did the following

Tag_1 <= Tag AND ( NOT ( Tag) ) ;

But its not working. I guess because of zero propagation delay of the
AND gate. I am using Spartan chip XC3S1000. Can anybody advice!

John

[palo]

I recently did it. I used the following code:

entity edge_detector is
port (clock, reset, kbint : in std_logic;
negative : out std_logic);
end edge_detector;

architecture Behavioral of edge_detector is

begin

detect : process (clock, reset)
variable rgst : std_logic_vector (1 downto 0);

begin
if reset = '1' then
rgst := "00";
negative <= '0';
elsif rising_edge(clock) then
if rgst = "01" then
negative <= '1';
else
negative <= '0';
end if;
rgst := kbint & rgst(1);
end if;
end process;

end Behavioral;

kbint is the input of which the edge I wanted to detect. This was a falling edge detector but you can modify this.

On 2 May 2007 08:44:30 -0700, john
<> wrote:

>I am trying to build a edge detector circuit. I did the following
>
>Tag_1 <= Tag AND ( NOT ( Tag) ) ;
>
>But its not working. I guess because of zero propagation delay of the
>AND gate. I am using Spartan chip XC3S1000. Can anybody advice!

Yes, most certainly.... DON'T TRY TO DO IT LIKE THAT.

Reason 1:
~~~~~~~~~
Consider what would happen if you were to get such a piece
of hardware working in the way you imagine it. The output
pulse would be approximately the same width as the NOT
operator's propagation delay. This is similar to the
propagation delay of everything else in your circuit,
and also similar to the RC time constant of typical
gate-to-gate wiring. Your pulse will be so narrow that
it is highly likely to disappear as it moves around
the device, and in any case it will be too narrow to
trigger any other logic reliably.

Reason 2:
~~~~~~~~~
The expression (Tag AND NOT Tag) is a simple function of
one input that can trivially be shown to be zero. Synthesis
will rather reliably turn it into a constant '0'.

Reason 3:
~~~~~~~~~
Why do you want to detect asynchronous edges on Tag? In
safe synchronous design methodology, the ONLY thing you ever
do with an asynchronous edge is use it to clock a flip-flop.


Re-work your design to resynchronise Tag to your clock and
then detect 0->1 transitions on it synchronously.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

john wrote:

> I am trying to build a edge detector circuit. I did the following
>
> Tag_1 <= Tag AND ( NOT ( Tag) ) ;
>
> But its not working. I guess because of zero propagation delay of the
> AND gate. I am using Spartan chip XC3S1000. Can anybody advice!

I always start with a synchronous process.
To create an edge detector, I would
declare an appropriate variable and
update it every clock edge with
a procedure like this

rising
(arg_in => retime_v.f3, -- USE the variable retime_v.f3
update => rising_v -- UPDATE the variable rising_v
);

See the source for details:
"Rising Level Counter"
http://home.comcast.net/~mike_treseler/

-- Mike Treseler

On May 2, 8:44 pm, john <conphil...@hotmail.com> wrote:
> Hi,
>
> I am trying to build a edge detector circuit. I did the following
>
> Tag_1 <= Tag AND ( NOT ( Tag) ) ;
>
> But its not working. I guess because of zero propagation delay of the
> AND gate. I am using Spartan chip XC3S1000. Can anybody advice!
>
> John

Try this...

process(clk, reset)
begin
if reset='1' then
inp_dly <= '0';
elsif rising_edge(clk) then
inp_dly <= inp;
end if;
end process;

inp_in_fall <= (not inp) and inp_dly; // input falling edge detection
inp_in_rise <= inp and (not inp_dly); // input rising edge detection

Regards,
JK

JK wrote:
> On May 2, 8:44 pm, john <conphil...@hotmail.com> wrote:
>> Hi,
>>
>> I am trying to build a edge detector circuit. I did the following
>>
>> Tag_1 <= Tag AND ( NOT ( Tag) ) ;
>>
>> But its not working. I guess because of zero propagation delay of the
>> AND gate. I am using Spartan chip XC3S1000. Can anybody advice!
>>
>> John
>
> Try this...
>
> process(clk, reset)
> begin
> if reset='1' then
> inp_dly <= '0';
> elsif rising_edge(clk) then
> inp_dly <= inp;
> end if;
> end process;
>
> inp_in_fall <= (not inp) and inp_dly; // input falling edge detection
> inp_in_rise <= inp and (not inp_dly); // input rising edge detection
>
> Regards,
> JK
>

Just a comment....
If the source of the input signal "inp" is not synchronous to your clock
you should add some extra registers in front of it to avoid metastable
conditions in your registers.

On May 3, 8:21 pm, Magne <magnem...@yahoo.no> wrote:
> JK wrote:
> > On May 2, 8:44 pm, john <conphil...@hotmail.com> wrote:
> >> Hi,
>
> >> I am trying to build a edge detector circuit. I did the following
>
> >> Tag_1 <= Tag AND ( NOT ( Tag) ) ;
>
> >> But its not working. I guess because of zero propagation delay of the
> >> AND gate. I am using Spartan chip XC3S1000. Can anybody advice!
>
> >> John
>
> > Try this...
>
> > process(clk, reset)
> > begin
> > if reset='1' then
> > inp_dly <= '0';
> > elsif rising_edge(clk) then
> > inp_dly <= inp;
> > end if;
> > end process;
>
> > inp_in_fall <= (not inp) and inp_dly; // input falling edge detection
> > inp_in_rise <= inp and (not inp_dly); // input rising edge detection
>
> > Regards,
> > JK
>
> Just a comment....
> If the source of the input signal "inp" is not synchronous to your clock
> you should add some extra registers in front of it to avoid metastable
> conditions in your registers.- Hide quoted text -
>
> - Show quoted text -

Yes, sorry I forgot to include this point. inp should be a
synchronized signal. A simple Dual-flop synchronizer is enough.

Regards,
JK