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Using signals in VHDL design

 
 
Sushma
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      05-02-2007
Dear friends:
I am new to VHDL and working on FPGA design of a Cyclone II
chip using Altera's Quartus II software. The problem I am having is
that I have limited number of ports and a lot of my inputs and outputs
to my D flip flops need to be defined as signals. But the problem is
that I am not able to do the design as signals are not getting
recognized as inputs or outputs to the flip-flops. Below is the
example of my code.

library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

ENTITY gates IS
PORT
(
RST :INOUT STD_LOGIC;
CLK :INOUT STD_LOGIC;
SRC :INOUT STD_LOGIC;
D0 :IN STD_LOGIC;
D1 :IN STD_LOGIC;
D2 :IN STD_LOGIC;
D3 :IN STD_LOGIC;
D4 :IN STD_LOGIC;
D5 :IN STD_LOGIC;
D6 :IN STD_LOGIC
);
END gates;

ARCHITECTURE behavior OF gates IS

SIGNAL A :STD_LOGIC;
SIGNAL B :STD_LOGIC;
SIGNAL C :STD_LOGIC;
SIGNAL D : STD_LOGIC;
SIGNAL E :STD_LOGIC;
SIGNAL F :STD_LOGIC;

SIGNAL INPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL OUTPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);


ATTRIBUTE keep: boolean;
ATTRIBUTE keep of A,B,C,D,E,F: SIGNAL IS true;


BEGIN


PROCESS(RST,CLK,D0,D1,D2,D3,INPUT_SIGNAL_1,OUTPUT_ SIGNAL_1)
BEGIN
INPUT_SIGNAL_1 <= (D0 & D1 & D2 & D3);
SRC<= OUTPUT_SIGNAL_1(3);
D <= OUTPUT_SIGNAL_1(2);
E<= OUTPUT_SIGNAL_1(1);
F <= OUTPUT_SIGNAL_1(0);
IF(RST='0')THEN
OUTPUT_SIGNAL_1 <= "0000";
ELSIF(CLK'EVENT AND CLK='1')THEN
OUTPUT_SIGNAL_1 <= INPUT_SIGNAL_1;
END IF;
END PROCESS;



PROCESS(RST,CLK)
BEGIN
IF(RST='0')THEN
A <='0';
B <='0';
C <='0';
ELSIF(CLK'EVENT AND CLK='1')THEN
A <=D4;
B <=D5;
C <=D6;
END IF;
END PROCESS;

END behavior;

My design does not work. Can you tell me what changes I need to make
so it works.

Thanks
Sushma

 
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Andy
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      05-02-2007
On May 2, 10:05 am, Sushma <(E-Mail Removed)> wrote:
> Dear friends:
> I am new to VHDL and working on FPGA design of a Cyclone II
> chip using Altera's Quartus II software. The problem I am having is
> that I have limited number of ports and a lot of my inputs and outputs
> to my D flip flops need to be defined as signals. But the problem is
> that I am not able to do the design as signals are not getting
> recognized as inputs or outputs to the flip-flops. Below is the
> example of my code.
>
> library IEEE ;
> use IEEE.std_logic_1164.all ;
> use IEEE.std_logic_arith.all ;
> use IEEE.std_logic_unsigned.all ;
>
> ENTITY gates IS
> PORT
> (
> RST :INOUT STD_LOGIC;
> CLK :INOUT STD_LOGIC;
> SRC :INOUT STD_LOGIC;
> D0 :IN STD_LOGIC;
> D1 :IN STD_LOGIC;
> D2 :IN STD_LOGIC;
> D3 :IN STD_LOGIC;
> D4 :IN STD_LOGIC;
> D5 :IN STD_LOGIC;
> D6 :IN STD_LOGIC
> );
> END gates;
>
> ARCHITECTURE behavior OF gates IS
>
> SIGNAL A :STD_LOGIC;
> SIGNAL B :STD_LOGIC;
> SIGNAL C :STD_LOGIC;
> SIGNAL D : STD_LOGIC;
> SIGNAL E :STD_LOGIC;
> SIGNAL F :STD_LOGIC;
>
> SIGNAL INPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
> SIGNAL OUTPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
>
> ATTRIBUTE keep: boolean;
> ATTRIBUTE keep of A,B,C,D,E,F: SIGNAL IS true;
>
> BEGIN
>
> PROCESS(RST,CLK,D0,D1,D2,D3,INPUT_SIGNAL_1,OUTPUT_ SIGNAL_1)
> BEGIN
> INPUT_SIGNAL_1 <= (D0 & D1 & D2 & D3);
> SRC<= OUTPUT_SIGNAL_1(3);
> D <= OUTPUT_SIGNAL_1(2);
> E<= OUTPUT_SIGNAL_1(1);
> F <= OUTPUT_SIGNAL_1(0);
> IF(RST='0')THEN
> OUTPUT_SIGNAL_1 <= "0000";
> ELSIF(CLK'EVENT AND CLK='1')THEN
> OUTPUT_SIGNAL_1 <= INPUT_SIGNAL_1;
> END IF;
> END PROCESS;
>
> PROCESS(RST,CLK)
> BEGIN
> IF(RST='0')THEN
> A <='0';
> B <='0';
> C <='0';
> ELSIF(CLK'EVENT AND CLK='1')THEN
> A <=D4;
> B <=D5;
> C <=D6;
> END IF;
> END PROCESS;
>
> END behavior;
>
> My design does not work. Can you tell me what changes I need to make
> so it works.
>
> Thanks
> Sushma


Don't mix combinatorial process and clocked process in one. You can do
the combinatorial behavior in a clocked process, but not like you've
shown. Review your synthesis tool documentation for example templates
of synthesizable processes.

What do you want your circuit to do? a,b,c,d,e,f all get assigned, but
go nowhere from there (i.e. to an output somewhere?)

The best I can tell, SRC is the only real output (clk and rst are
inout???), and it gets driven by a clocked (registered) version of D0.
So other than them and the clock and reset, everything else is getting
optimized away because it is not used. It is not enough to just
reference an input signal or port. It actually has to feed into an
output (or something that in turn feeds into an output, etc) somehow
in order to not get optimized away. "keep" will do nothing for you in
this situation.

Andy

 
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JK
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Posts: n/a
 
      05-03-2007
On May 2, 8:05 pm, Sushma <(E-Mail Removed)> wrote:
> Dear friends:
> I am new to VHDL and working on FPGA design of a Cyclone II
> chip using Altera's Quartus II software. The problem I am having is
> that I have limited number of ports and a lot of my inputs and outputs
> to my D flip flops need to be defined as signals. But the problem is
> that I am not able to do the design as signals are not getting
> recognized as inputs or outputs to the flip-flops. Below is the
> example of my code.
>
> library IEEE ;
> use IEEE.std_logic_1164.all ;
> use IEEE.std_logic_arith.all ;
> use IEEE.std_logic_unsigned.all ;
>
> ENTITY gates IS
> PORT
> (
> RST :INOUT STD_LOGIC;
> CLK :INOUT STD_LOGIC;
> SRC :INOUT STD_LOGIC;
> D0 :IN STD_LOGIC;
> D1 :IN STD_LOGIC;
> D2 :IN STD_LOGIC;
> D3 :IN STD_LOGIC;
> D4 :IN STD_LOGIC;
> D5 :IN STD_LOGIC;
> D6 :IN STD_LOGIC
> );
> END gates;
>
> ARCHITECTURE behavior OF gates IS
>
> SIGNAL A :STD_LOGIC;
> SIGNAL B :STD_LOGIC;
> SIGNAL C :STD_LOGIC;
> SIGNAL D : STD_LOGIC;
> SIGNAL E :STD_LOGIC;
> SIGNAL F :STD_LOGIC;
>
> SIGNAL INPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
> SIGNAL OUTPUT_SIGNAL_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
>
> ATTRIBUTE keep: boolean;
> ATTRIBUTE keep of A,B,C,D,E,F: SIGNAL IS true;
>
> BEGIN
>
> PROCESS(RST,CLK,D0,D1,D2,D3,INPUT_SIGNAL_1,OUTPUT_ SIGNAL_1)
> BEGIN
> INPUT_SIGNAL_1 <= (D0 & D1 & D2 & D3);
> SRC<= OUTPUT_SIGNAL_1(3);
> D <= OUTPUT_SIGNAL_1(2);
> E<= OUTPUT_SIGNAL_1(1);
> F <= OUTPUT_SIGNAL_1(0);
> IF(RST='0')THEN
> OUTPUT_SIGNAL_1 <= "0000";
> ELSIF(CLK'EVENT AND CLK='1')THEN
> OUTPUT_SIGNAL_1 <= INPUT_SIGNAL_1;
> END IF;
> END PROCESS;
>
> PROCESS(RST,CLK)
> BEGIN
> IF(RST='0')THEN
> A <='0';
> B <='0';
> C <='0';
> ELSIF(CLK'EVENT AND CLK='1')THEN
> A <=D4;
> B <=D5;
> C <=D6;
> END IF;
> END PROCESS;
>
> END behavior;
>
> My design does not work. Can you tell me what changes I need to make
> so it works.
>
> Thanks
> Sushma


Your code is a bit messy. It happens for a beginner.

I guess D0, D1...D6 are inputs and SRC is output apart from reset &
clock (these are inputs, dont declare them as inout).
What functionality you are looking for???

Regards,
JK




 
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