fast synthesize

vbehravan

Junior Member

Join Date: Nov 2006

Posts: 4

04-30-2007

hi all,
when I change my VHDL code a little (i.e. replace a<=not(b) with a<=b)
and synthesize the code, all of sequences in ISE(translate,map,place and route,...) do from first to make .bit file and takes several minuits to complete.
I expect since I changed only a little portion of hardware, ISE only change this section(in transleta,map and place&route) and make .bit file soon.
is there any solution to make .bit file very fast for little change in code?
regards.

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