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Re: VHDL syntax

 
 
Andy
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      04-24-2007
On Apr 23, 4:36 pm, Jim Lewis <(E-Mail Removed)> wrote:
> Grumps,
>
> > What synthesiser feature/specification suggests compliance?

>
> IEEE 1076.6 specifies VHDL RTL Coding. Unfortunately 1076.6-2004
> (the most current) states:
> For a discrete range that appears as part of a slice name,
> the bounds of the discrete range shall be specified
> directly or indirectly as static values belonging to an
> integer type.
>
> I am not sure about your application, but for some of mine,
> this needs to be updated.
>
> In general, if you have issues of language compliance, in which
> different vendors disagree or you and a vendor disagree, and
> you can get cooperation from the vendor, you can
> also get an official language resolution from the VHDL Issues
> Screening and Analysis Committee (ISAC). Please make sure to
> keep the vendor's name out of the issue report - the ISAC worries
> about compliance - once you receive the compliance report, you
> can deal with the vendor. =You can report issues to ISAC at:
> http://www.eda-stds.org/vasg/#Enhancements
>
> For synthesis issues click on: "Report a BUG on an IEEE VHDL revision"
>
> Best Regards,
> Jim Lewis
> IEEE VHDL and Analysis Standards Group (VASG) Chair
> SynthWorks VHDL Training


While most synthesis tools will accept non-static expression in
ranges, they also usually must implement the computational circuitry
for those expressions in hardware.

If it is possible to code it in a for loop with an if statement,
comparing the unadulterated signal to an expression of the index, then
the index is treated as if "static" when the loop is unrolled, and the
computation of the expression is not done in hardware. Therefore such
expressions are also not limited by what is implementable in hardware
(i.e. divide/modulo by non-integral-powers of two, etc.).

Andy

 
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