Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Signal zaehl cannot be synthesized

Thread Tools

Signal zaehl cannot be synthesized

Reload6156 Reload6156 is offline
Junior Member
Join Date: Apr 2007
Posts: 2
Hi Guys! I've got a problem with my vhdl code. I am very new at programming in this language and for this reason i am not be able to find the mistake. I tried hard without success. Signal zaehl cannot be synthesized, bad synchronous description. I hope somebody can help me. Furthermore, this project must be programmed at school.

ENTITY zaehler IS
PORT ( clock, zuendung, automatik : in std_logic;
katnr, rauf, runter ,sperr_ext :in bit;
leda, ledb, ledc, ledd, lede, ledf, ledg, dp, ledrauf, ledrunter, ledkatnr, transistor1, transistor2 ut bit);
END zaehler ;

ARCHITECTURE number_one OF zaehler IS

signal gang : std_logic_vector (2 downto 0);
signal zaehl : std_logic_vector (5 downto 0);-- badsynchronous description
signal zaehl_sperr : std_logic_vector (6 downto 0);
signal zaehl_auto : std_logic_vector (7 downto 0);
signal gang_alt : std_logic_vector (2 downto 0);


PROCESS (clock, zuendung, automatik, katnr, zaehl, zaehl_sperr, zaehl_auto, gang, gang_alt, rauf, runter, sperr_ext)
transistor1 <= '0';
transistor2 <= '1';
gang <= "001";
zaehl<= "000000";
zaehl_sperr <= "1010101";
zaehl_auto <= "00000000";
Reply With Quote
martin.wahlstedt martin.wahlstedt is offline
Junior Member
Join Date: Mar 2007
Posts: 14
Remove the signals zaehl, zaehl_sperr, zaehl_auto, gang & gang_alt from the sensitivity list and the problem should be solved. Put only signals that you want your process to trigger on, for instance clock and reset for a synchronous architecture, in the sensitivity list.

The reason you get the error on 'zaehl' is probably because it is the first one in the list.

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
cannot be synthesized uche VHDL 4 04-06-2010 03:11 PM
cannot be synthesized, bad synchronous description Zenock VHDL 7 03-10-2010 10:16 AM
VHDL problem - Signal counter cannot be synthesized, bad synchronous description. shipacpoloy Software 0 08-14-2007 06:26 AM
Converting synthesized VHDL/Verilog to spice netlist Noohul Ali VHDL 2 04-28-2005 11:25 AM
Quartus II v3, Circuit after synthesized? Aoniti VHDL 1 05-25-2004 05:26 PM