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VHDL - Use BRam and DRam on FPGA's Xilinx |
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04-16-2007, 03:27 AM
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#1 |
Use BRam and DRam on FPGA's Xilinx
Hi everybody!
When I write verilog code to generate RAM or ROM, the source code only use slices resources. But I want to use BRam or DRam resources on FPGA (FPGA's Xilinx) to generate RAM or ROM. Can you help me? Gordon Freeman |
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04-16-2007, 01:42 PM
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#2 |
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Posts: n/a
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Re: Use BRam and DRam on FPGA's Xilinx
The most common reason people get flops/gates when the wanted RAM is
that they are reading/writing more than one (single port) or two (dual port) elements of the same array in the same clock cycle. Review your code to ensure this is not happening. Andy On Apr 15, 9:27 pm, "Gordon Freeman" <gordonfreeman1...@gmail.com> wrote: > Hi everybody! > When I write verilog code to generate RAM or ROM, the source code only > use slices resources. But I want to use BRam or DRam resources on FPGA > (FPGA's Xilinx) to generate RAM or ROM. Can you help me? Andy |
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04-16-2007, 03:02 PM
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#3 |
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Junior Member
Join Date: Mar 2007
Posts: 14
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google xst.pdf and read the pages about memories, p. 120 ->
Martin martin.wahlstedt |
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04-17-2007, 10:53 PM
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#4 |
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Posts: n/a
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Re: Use BRam and DRam on FPGA's Xilinx
On Apr 15, 7:27 pm, "Gordon Freeman" <gordonfreeman1...@gmail.com>
wrote: > Hi everybody! > When I write verilog code to generate RAM or ROM, the source code only > use slices resources. But I want to use BRam or DRam resources on FPGA > (FPGA's Xilinx) to generate RAM or ROM. Can you help me? Depending on the FPGA family, you need to describe a synchronous read in order to infer a BRAM. -a Andy Peters |
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04-18-2007, 10:47 AM
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#5 |
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Re: Use BRam and DRam on FPGA's Xilinx
Hi!
Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding techniques. This chapter describes detailed which HDL constructs will result in the usage of which FPGA resource. Matthias Gordon Freeman schrieb: > Hi everybody! > When I write verilog code to generate RAM or ROM, the source code only > use slices resources. But I want to use BRam or DRam resources on FPGA > (FPGA's Xilinx) to generate RAM or ROM. Can you help me? > Matthias Alles |
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04-23-2007, 03:51 AM
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#6 |
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Posts: n/a
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Re: Use BRam and DRam on FPGA's Xilinx
On Apr 18, 4:47 pm, Matthias Alles <REMOVEallesCAPIT...@NOeit.SPAMuni-
kl.de> wrote: > Hi! > > Take a look at the XST manual (xst.pdf), chapter 2: HDL Coding > techniques. This chapter describes detailed which HDL constructs will > result in the usage of which FPGA resource. > > Matthias > > Gordon Freeman schrieb: > > > Hi everybody! > > When I write verilog code to generate RAM or ROM, the source code only > > use slices resources. But I want to use BRam or DRam resources on FPGA > > (FPGA's Xilinx) to generate RAM or ROM. Can you help me? Thank you. Right now, I can make it. Gordon Freeman |
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