Script to Expand Buses and Ports?

Hi:

I'm wondering if anyone knows of a script of program which will expand
the buses and ports? I'm looking to create a symbol from a VHDL module
and having a great deal of problems. Some of the code I would need to
handle:

o_pin_top_sdram_clk_en : out std_logic;

not a problem, one output pin.

i_pin_bottom_fedback_clk_in : in std_logic_vector(1 downto 0);

All right, two bits 1 and 0 on an input pin...

io_pin_sdram_dqs : inout
std_logic_vector((get_Memdqstapwidth(Mem_array_wid th,
SDRAM_DATA_WIDTH, Parity_present)*SDRAM_DATA_WIDTH/ - 1 downto 0) ;

What the ???

I'm not a VHDL coder, just trying to generate a symbol. I'm wondering
if anyone knows of a tool or script or Perl Module which could parse
this and bit blast it out.

Thanks for any help.

Tom

g4173c@motorola.com

On 13 Apr 2007 05:19:20 -0700, wrote:

>Hi:
>
>I'm wondering if anyone knows of a script of program which will expand
>the buses and ports? I'm looking to create a symbol from a VHDL module
>
>io_pin_sdram_dqs : inout
>std_logic_vector((get_Memdqstapwidth(Mem_array_wi dth,
>SDRAM_DATA_WIDTH, Parity_present)*SDRAM_DATA_WIDTH/ - 1 downto 0) ;
>
>What the ???

A nice general piece of code

It's a bus. Its width is not known until elaboration time.

Unless you can compile all the VHDL (not just this module, but
all of it) and evaluate the constant function get_Memdqstapwidth(),
you have no way to know the size of the bus.

It may be easier to run the design through front-end synthesis,
and then ask the synthesis tool what it thinks about the port.

That's why we use HDLs rather than diagrams these days.
--
Jonathan Bromley, Consultant

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