Not able to figure out the error.. Need help

A very simple program of mine where I am making an assignment of '1'
to a signal is giving me the following problem: The signal,instead of
accepting '1' as the value,takes 'X'(forced unknown in std_logic).
This is during simulation in MODELSIM or in the ISE testbench in
Xilinx.

Also, another program of mine,with similar assignment of values to
a Std_logic Signal,on synthesis, is giving the error-'Multi Source In
Unit <Unit Name> '..

I have constantly been trying to figure out the solution for these
problems but have as yet been unsuccessful.



Would really appreciate the help.

Thanks,

Shashank.

shashank

You are probably driving the same signal from more than one process
(and concurrent assignments are their own processes). If all drivers
do not agree, you can get a resulting 'X' on the signal.

Also, if an entity has the signal tied to one of its inout ports, that
entity creates a driver for it, even if there is no assignment to that
port within the corresponding architecture.

Andy

On Apr 11, 2:03 pm, "shashank" <shashank.kalm...@gmail.com> wrote:
> A very simple program of mine where I am making an assignment of '1'
> to a signal is giving me the following problem: The signal,instead of
> accepting '1' as the value,takes 'X'(forced unknown in std_logic).
> This is during simulation in MODELSIM or in the ISE testbench in
> Xilinx.
>
> Also, another program of mine,with similar assignment of values to
> a Std_logic Signal,on synthesis, is giving the error-'Multi Source In
> Unit <Unit Name> '..
>
> I have constantly been trying to figure out the solution for these
> problems but have as yet been unsuccessful.
>
> Would really appreciate the help.
>
> Thanks,
>
> Shashank.

Andy

In Modelsim, you can use the command

drivers <signal path/signal name>

to get a list of all the drivers attached to a given signal along with
the values they are driving.
Very useful feature

On Apr 11, 2:18 pm, "Andy" <jonesa...@comcast.net> wrote:
> You are probably driving the same signal from more than one process
> (and concurrent assignments are their own processes). If all drivers
> do not agree, you can get a resulting 'X' on the signal.

canadianJaouk

canadianJaouk wrote:

> In Modelsim, you can use the command
>
> drivers <signal path/signal name>
>
> to get a list of all the drivers attached to a given signal along
> with the values they are driving.
> Very useful feature

Yes indeed. Even more useful yet: use std_ulogic in stead of std_logic
for single bit signals. Then you get an error during compilation,
because std_ulogic is an unresolved type, so not allowing multiple
drivers.

--
Paul.
www.aimcom.nl
email address: switch x and s

Paul Uiterlinden

Paul Uiterlinden wrote:

> Yes indeed. Even more useful yet: use std_ulogic in stead of std_logic
> for single bit signals. Then you get an error during compilation,
> because std_ulogic is an unresolved type, so not allowing multiple
> drivers.


Yes. And unless the signal is a tri-state node or a vector,
there is no reason *not* to use std_ulogic, other than tradition.
Std_ulogic port maps directly to std_logic without conversion.


-- Mike Treseler

Mike Treseler

On Apr 17, 4:45 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> Paul Uiterlinden wrote:
> > Yes indeed. Even more useful yet: use std_ulogic in stead of std_logic
> > for single bit signals. Then you get an error during compilation,
> > because std_ulogic is an unresolved type, so not allowing multiple
> > drivers.
>
> Yes. And unless the signal is a tri-state node or a vector,
> there is no reason *not* to use std_ulogic, other than tradition.
> Std_ulogic port maps directly to std_logic without conversion.
>
> -- Mike Treseler

And they've changed the way std_logic_vector is defined (backwards
compatible) to allow similar interfacing with std_ulogic_vector. This
is in Accellera 2006 std, I believe.

Andy

Andy