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VHDL - Command Decoder?

 
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Old 04-06-2007, 07:40 PM   #1
Default Command Decoder?


Hello all,

I'm a new member and fairly new to VHDL. I have a question and I was hoping someone can help? I'm trying to write a command decoder for a communication protocol. The decoder reads in the last 5 bits of the data line and outputs the corresponding commands based on the defined bits/constants. The problem I have is with the first Signal : PON (Power On Reset). The requirement is that if the local pon message is already asserted, the pon command (once again written) simply has to clear the local pon message. How do I do that?

Here is what I have:

DECODER: PROCESS (I_HRST, I_DIN)

BEGIN

IF (I_HRST = '0') THEN

I_IEPON <= '0';
O_SRST <= '0';
.
.
.
.

ELSE

CASE I_DIN (4 DOWNTO 0) IS

WHEN IEPON_C =>

I_IEPON <= '1';

WHEN SRST_C =>

O_SRST <= '1';
.
.
.
.
.

WHEN OTHERS =>

NULL;

END CASE;

END IF;

END PROCESS; -- DECODER

Any help will be greatly appreciated.


Unity
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Old 04-06-2007, 09:13 PM   #2
Unity
Junior Member
 
Join Date: Apr 2007
Posts: 4
Default
Never mind everyone. I figured it out. I changed my process from Case Statement to If Statements. Then I created a dummy signal I_IEPON so that my dummy signal is readback before it is assigned to the output port. Here it is:

O_IEPON <= I_IEPON;

PROCESS (HRST, I_DIN)

BEGIN

IF (HRST = '0') THEN

I_IEPON <= '0';

ELSIF (I_DIN (4 DOWNTO 0) = "00000") THEN

I_IEPON <= '1' XOR I_IEPON;

ELSE
NULL;
END IF;

END PROCESS;

When I simulate my design it works. On the first demand, it activates IEPON and on the second demand, it deactivates. Now my question is whats the difference? Why it didn't work when using case Statement?

Unity


Unity
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