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Hi,
In my many projects, some signals have both positive reference and
negative reference, does it cause an additional LUT delay?

For example, in the following statement Rx and not Rx are both used
and they cannot be put together by a LUT.

A1 : process(CLK)
begin
if(CLK'event and CLK = '1') then
A <= Sx;
end if;
end process;

A2 : process(CLK)
begin
if(CLK'event and CLK = '1') then
B <= not Sx;
end if;
end process;

Sx may be a combinational signal or a flip-flop output.

I am wondering whether Xilinx interconnect resources is capable of
inversing a passing signal based on the need.

Thank you.

Weng

"Weng Tianxiang" <> wrote in message
news: oups.com...
> Hi,
> In my many projects, some signals have both positive reference and
> negative reference, does it cause an additional LUT delay?
Are you talking about differential signals? If so, most newer parts support
differential I/O signals directly although many, if not most, might only be
the lower voltage form, LVDS (which is usually what you want...but not
always). In any case, this support is generally 'free' in that it is simply
an I/O standard so there is no additional delay incurred in generating each
half of the differential pair.

>
> For example, in the following statement Rx and not Rx are both used
> and they cannot be put together by a LUT.
>
> A1 : process(CLK)
> begin
> if(CLK'event and CLK = '1') then
> A <= Sx;
> end if;
> end process;
>
> A2 : process(CLK)
> begin
> if(CLK'event and CLK = '1') then
> B <= not Sx;
> end if;
> end process;
>
If you are talking about differential I/O, then you wouldn't explicitly
write equations for each output, just the 'positive' half (which in the
above case appears to be signal 'A'. You would then specify that 'A' is a
differential pair and there would then be two physical pins assigned, one to
each half.

Depending on the actual targetted part, there might be restrictions about
just which pins can be differential and which can not and once you've picked
the physical pin for the 'positive half' of the pair that also implicitly
picks the pin for the 'negative half' as well.

>
> I am wondering whether Xilinx interconnect resources is capable of
> inversing a passing signal based on the need.
>
Not sure what you mean, but maybe the answer is in what I've already posted.

Kevin Jennings

Weng, there are no inverters in the interconnect structure.
But the obvious flexibility of a ROM=LUT means that you can fold the
inversion into the LUT.
Remember, LUTs have 4 inputs and one output, except in Virtex-5, where
they have 6-inputs and one output, but can optionally have 5 inputs
and 2 outputs.
I think you can figure out the rest.
Peter Alfke, Xilinx
================
On Mar 17, 11:11 am, "Weng Tianxiang" <wtx...@gmail.com> wrote:
> Hi,
> In my many projects, some signals have both positive reference and
> negative reference, does it cause an additional LUT delay?
>
> For example, in the following statement Rx and not Rx are both used
> and they cannot be put together by a LUT.
>
> A1 : process(CLK)
> begin
> if(CLK'event and CLK = '1') then
> A <= Sx;
> end if;
> end process;
>
> A2 : process(CLK)
> begin
> if(CLK'event and CLK = '1') then
> B <= not Sx;
> end if;
> end process;
>
> Sx may be a combinational signal or a flip-flop output.
>
> I am wondering whether Xilinx interconnect resources is capable of
> inversing a passing signal based on the need.
>
> Thank you.
>
> Weng

On Mar 17, 5:12 pm, "Peter Alfke" <a...@sbcglobal.net> wrote:
> Weng, there are no inverters in the interconnect structure.
> But the obvious flexibility of a ROM=LUT means that you can fold the
> inversion into the LUT.
> Remember, LUTs have 4 inputs and one output, except in Virtex-5, where
> they have 6-inputs and one output, but can optionally have 5 inputs
> and 2 outputs.
> I think you can figure out the rest.
> Peter Alfke, Xilinx
> ================
> On Mar 17, 11:11 am, "Weng Tianxiang" <wtx...@gmail.com> wrote:
>
>
>
> > Hi,
> > In my many projects, some signals have both positive reference and
> > negative reference, does it cause an additional LUT delay?
>
> > For example, in the following statement Rx and not Rx are both used
> > and they cannot be put together by a LUT.
>
> > A1 : process(CLK)
> > begin
> > if(CLK'event and CLK = '1') then
> > A <= Sx;
> > end if;
> > end process;
>
> > A2 : process(CLK)
> > begin
> > if(CLK'event and CLK = '1') then
> > B <= not Sx;
> > end if;
> > end process;
>
> > Sx may be a combinational signal or a flip-flop output.
>
> > I am wondering whether Xilinx interconnect resources is capable of
> > inversing a passing signal based on the need.
>
> > Thank you.
>
> > Weng- Hide quoted text -
>
> - Show quoted text -

Hi Peter,
Thank you for your answer. Your answer is good enough to meet my
curiosity.

1. Interconnect has no inverter;
2. Any inverted signals will be absorbed by a LUT.

I very much appreciate Peter's EXCELLENT service for Xilinx company as
an expert to answer all questions none of Xilinx clients can
satisfactorily and authoritatively answers.

Weng

Weng Tianxiang wrote:
>
> Hi Peter,
> Thank you for your answer. Your answer is good enough to meet my
> curiosity.
>
> 1. Interconnect has no inverter;
> 2. Any inverted signals will be absorbed by a LUT.
>
> I very much appreciate Peter's EXCELLENT service for Xilinx company as
> an expert to answer all questions none of Xilinx clients can
> satisfactorily and authoritatively answers.
>
> Weng
>

Not *all* inverters must be absorbed by LUTs. I'm worried you'll take
this answer too far.

The SLICEs and IOBs both have a significant amount of control over
inversions for input signals. If you open a design with FPGA Editor,
you'll see many of the signals in the SLICE and IOB (even the BlockRAMs
and Multipliers) such as clock, reset, the direct-input BX and BY
values, and most of the signals *except* for the LUT inputs have a
normal/invert option where the invert gets absorbed into the SLICE. The
data and address into BlockRAMs and arguements of the multiply might not
have automatic inversion available but their control signals mostly do.

The one condition I recall having to pay attention to the signal
polarity in general logic - where it can affect timing - is when going
in to a carry chain as a direct input to the MUXCY primitive. I can
infer an add or subtract fine, but sometimes a needed inversion results
in an extra LUT of delay before coming onto the carry chain because the
..DI (or MULT_AND) inputs can't absorb the input. Often it's just a
matter of producing an inverted form of the registers that feed the
logic; this is sometimes referred to as "not gate push-back" if it's
handled for you by the synthesizer.

- John_H

On Mar 18, 11:14 am, John_H <newsgr...@johnhandwork.com> wrote:
> Weng Tianxiang wrote:
>
> > Hi Peter,
> > Thank you for your answer. Your answer is good enough to meet my
> > curiosity.
>
> > 1. Interconnect has no inverter;
> > 2. Any inverted signals will be absorbed by a LUT.
>
> > I very much appreciate Peter's EXCELLENT service for Xilinx company as
> > an expert to answer all questions none of Xilinx clients can
> > satisfactorily and authoritatively answers.
>
> > Weng
>
> Not *all* inverters must be absorbed by LUTs. I'm worried you'll take
> this answer too far.
>
> The SLICEs and IOBs both have a significant amount of control over
> inversions for input signals. If you open a design with FPGA Editor,
> you'll see many of the signals in the SLICE and IOB (even the BlockRAMs
> and Multipliers) such as clock, reset, the direct-input BX and BY
> values, and most of the signals *except* for the LUT inputs have a
> normal/invert option where the invert gets absorbed into the SLICE. The
> data and address into BlockRAMs and arguements of the multiply might not
> have automatic inversion available but their control signals mostly do.
>
> The one condition I recall having to pay attention to the signal
> polarity in general logic - where it can affect timing - is when going
> in to a carry chain as a direct input to the MUXCY primitive. I can
> infer an add or subtract fine, but sometimes a needed inversion results
> in an extra LUT of delay before coming onto the carry chain because the
> .DI (or MULT_AND) inputs can't absorb the input. Often it's just a
> matter of producing an inverted form of the registers that feed the
> logic; this is sometimes referred to as "not gate push-back" if it's
> handled for you by the synthesizer.
>
> - John_H

Hi John,
Thank you for your advice. I am reading Virtex-5 CLB block diagram
now. It is no doubt that the better the FPGA internal structure is
understood, the high performance one can achieve.


Weng

John_H wrote:

> The one condition I recall having to pay attention to the signal
> polarity in general logic - where it can affect timing - is when going
> in to a carry chain as a direct input to the MUXCY primitive. I can
> infer an add or subtract fine, but sometimes a needed inversion results
> in an extra LUT of delay before coming onto the carry chain because the
> .DI (or MULT_AND) inputs can't absorb the input. Often it's just a
> matter of producing an inverted form of the registers that feed the
> logic; this is sometimes referred to as "not gate push-back" if it's
> handled for you by the synthesizer.
>
> - John_H

I believe that particular "feature" has been addressed in the V5 carry
chain structure so that now you have a LUT-like programmability in place
of the former MULT_AND primitive on the MUXCY DI input. Yes, this
particular thing has been the source of many not-so-obvious work-arounds
to avoid having a non-absorbable inverter messing up the timing closure.